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july 2003 the following document specifies spansion memory products that are now offered by both advanced micro devices and fujitsu. although the document is marked with the name of the company that orig- inally developed the specification, these products will be offered to cu stomers of both amd and fujitsu. continuity of specifications there is no change to this datasheet as a result of offering the device as a spansion product. any changes that have been made are the result of normal datasheet improvement and are noted in the document revision summary, where supported. futu re routine revisions will occur when appropriate, and changes will be noted in a revision summary. continuity of ordering part numbers amd and fujitsu continue to support existing part numbers beginning with ?am? and ?mbm?. to order these products, please use on ly the ordering part numbers listed in this document. for more information please contact your local amd or fujitsu sales office for additional information about spansion memory solutions. am41lv3204m data sheet publication number 30119 revision a amendment +1 issue date june 10, 2003
preliminary this document contains information on a product under development at advanced micro devices. the information is intended to help you evaluate this product. amd reserves the right to change or discontinue work on this proposed product without notice. publication# 30119 rev: a amendment/ +1 issue date: june 10, 2003 refer to amd?s website (www.amd.com) for the latest information. am41lv3204m stacked multi-chip package (mcp) 32 mbit (4 m x 8 bit/2 m x 16-bit) flash memory and 4 mbit (512k x 8-bit/256 k x 16-bit) static ram distinctive characteristics mcp features power supply voltage of 2.7 to 3.3 volt high performance ? access time as fast as 100ns initial 30 ns page flash 70 ns sram package ? 69-ball fbga ? 8 x 10 x 1.2 mm operating temperature ??40 c to +85 c flash memory features architectural advantages single power supply operation ? 3 v for read, erase, and program operations manufactured on 0.23 m mirrorbit process technology secsi ? (secured silicon) sector region ? 128-word/256-byte sector for permanent, secure identification through an 8-word/16-byte random electronic serial number, accessible through a command sequence ? may be programmed and locked at the factory or by the customer flexible sector architecture ? sixty-three 32 kword/64-kbyte sectors ? eight 4 kword/8-kbyte boot sectors compatibility with jedec standards ? provides pinout and software compatibility for single-power supply flash, and superior inadvertent write protection minimum 100,000 erase cycle guarantee per sector 20-year data retention at 125 c performance characteristics high performance ? 100 ns access time ? 30 ns page read times ? 0.5 s typical sector erase time ? 15 s typical write buffer word programming time: 16-word/32-byte write buffer reduces overall programming time for multiple-word updates ? 4-word/8-byte page read buffer ? 16-word/32-byte write buffer low power consumption (typical values at 3.0 v, 5 mhz) ? 30 ma typical initial page read current; 10 ma typical intra-page read current ? 50 ma typical erase/program current ? 1 a typical standby mode current software & hardware features software features ? program suspend & resume: read other sectors before programming operation is completed ? erase suspend & resume: read/program other sectors before an erase operation is completed ? data# polling & toggle bits provide status ? unlock bypass program command reduces overall multiple-word programming time ? cfi (common flash interface) compliant: allows host system to identify and accommodate multiple flash devices hardware features ? sector group protection: hardware-level method of preventing write operations within a sector group ? temporary sector unprotect: v id -level method of changing code in locked sectors ? wp#/acc input: write protect input (wp#) protects top or bottom two sectors regardless of sector protection settings acc (high voltage) accelerates programming time for higher throughput during system production ? hardware reset input (reset#) resets device sram features power dissipation ? operating: 30 ma maximum ? standby: 10 a maximum ce1s# and ce2s chip select power down features using ce1s# and ce2s data retention supply voltage: 1.5 to 3.3 volt byte data control: lb#s (dq7?dq0), ub#s (dq15?dq8)
2 am41lv3204m june 10, 2003 preliminary general description am29lv320mt features the am29lv320mt/b is a 32 mbit, 3.0 volt single power supply flash memory device organized as 2,097,152 words or 4,194,304 bytes. the device has an 8/16-bit bus and can be programmed either in the host system or in standard eprom programmers. word mode data appears on dq15?dq0. the device is designed to be programmed in-system with the standard 3.0 volt v cc supply, and can also be pro- grammed in standard eprom programmers. lv320mt/b has an access time of 100 ns. note that the access time has a specific operating voltage range (v cc ) as specified in the product selector guide and the ordering information sections. the device is of- fered in a 69-ball fine pitch bga. the devices require only a single 3.0 volt power sup- ply for both read and write functions. internally gener- ated and regulated voltages are provided for the program and erase operations. the device is entirely command set compatible with the jedec single-power-supply flash standard . commands are written to the device using standard microprocessor write timing. write cycles also inter- nally latch addresses and data needed for the pro- gramming and erase operations. the sector erase architecture allows memory sec- tors to be erased and reprogrammed without affecting the data contents of other sectors. the device is fully erased when shipped from the factory. device programming and erasure are initiated through command sequences. once a program or erase oper- ation has begun, the host system need only poll the dq7 (data# polling) or dq6 (toggle) status bits or monitor the ready/busy# (ry/by#) output to deter- mine whether the operation is complete. to facilitate programming, an unlock bypass mode reduces com- mand sequence overhead by requiring only two write cycles to program data instead of four. hardware data protection measures include a low v cc detector that automatically inhibits write opera- tions during power transitions. the hardware sector protection feature disables both program and erase operations in any combination of sectors of memory. this can be achieved in-system or via programming equipment. the erase suspend/erase resume feature allows the host system to pause an erase operation in a given sector to read or program any other sector and then complete the erase operation. the program suspend/program resume feature enables the host system to pause a program operation in a given sector to read any other sector and then complete the pro- gram operation. the hardware reset# pin terminates any operation in progress and resets the device, after which it is then ready for a new operation. the reset# pin may be tied to the system reset circuitry. a system reset would thus also reset the device, enabling the host system to read boot-up firmware from the flash memory device. the device reduces power consumption in the standby mode when it detects specific voltage levels on ce# and reset#, or when addresses have been stable for a specified period of time. the write protect (wp#) feature protects the top or bottom two sectors by asserting a logic low on the wp#/acc pin. the protected sector will still be pro- tected even during accelerated programming. the secsi ? (secured silicon) sector provides a 128-word/256-byte area for code or data that can be permanently protected. once this sector is protected, no further changes within the sector can occur. amd mirrorbit flash technology combines years of flash memory manufacturing experience to produce the highest levels of quality, reliability and cost effec- tiveness. the device electrically erases all bits within a sector simultaneously via hot-hole assisted erase. the data is programmed using hot electron injection.
june 10, 2003 am41lv3204m 3 preliminary table of contents product selector guide . . . . . . . . . . . . . . . . . . . . . 4 mcp block diagram . . . . . . . . . . . . . . . . . . . . . . . . 4 flash memory block diagram. . . . . . . . . . . . . . . . 5 connection diagrams . . . . . . . . . . . . . . . . . . . . . . 6 pin description. . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 ordering information . . . . . . . . . . . . . . . . . . . . . . . 8 device bus operations . . . . . . . . . . . . . . . . . . . . . 9 table 2. device bus operations?flash word mode, ciof = vih, sram word mode, cios = v il ......................................................11 table 3. device bus operations?flash byte mode, ciof = v ss ; sram word mode, cios = v cc .....................................................12 table 4. device bus operations?flash byte mode, ciof = v il ; sram byte mode, cios = v ss ..................................................................13 requirements for reading array data ................................... 14 page mode read .................................................................... 14 writing commands/command sequences ............................ 14 write buffer ............................................................................. 14 accelerated program operation ............................................. 14 autoselect functions .............................................................. 14 automatic sleep mode ........................................................... 15 reset#: hardware reset pin ............................................... 15 output disable mode .............................................................. 15 ................................................................................................ 16 sector group protection and unprotec tion ............................. 18 table 6. am29lv320mt top boot sector protection .....................18 ................................................................................................ 18 table 7. am29lv320mb bottom boot sector protection ................18 write protect (wp#) ................................................................ 18 temporary sector group u nprotect ....................................... 19 figure 1. temporary sector group unprotect operation................ 19 figure 2. in-system sector group protect/unprotect algorithms ... 20 secsi (secured silicon) sector flash memory region .......... 21 table 8. secsi sector contents ......................................................21 figure 3. secsi sector protect verify.............................................. 22 hardware data protection ...................................................... 22 low vcc write inhibit ............................................................ 22 write pulse ?glitch? protection ............................................... 22 logical inhibit .......................................................................... 22 power-up write inhibit ............................................................ 22 common flash memory interface (cfi) . . . . . . . 22 command definitions . . . . . . . . . . . . . . . . . . . . . 25 reading array data ................................................................ 25 reset command ..................................................................... 26 autoselect command sequence ............................................ 26 enter secsi sector/exit secsi sector command sequence .. 26 word program command sequence ..................................... 26 unlock bypass command sequence ..................................... 27 write buffer programming ...................................................... 27 accelerated program .............................................................. 28 figure 4. write buffer programming operation............................... 29 figure 5. program operation .......................................................... 30 program suspend/program resume command sequence ... 30 figure 6. program suspend/program resume............................... 31 chip erase command sequence ........................................... 31 sector erase command sequence ........................................ 31 figure 7. erase operation............................................................... 32 erase suspend/erase resume commands ........................... 32 write operation status . . . . . . . . . . . . . . . . . . . . 35 dq7: data# polling ................................................................. 35 figure 8. data# polling algorithm .................................................. 35 dq6: toggle bit i .................................................................... 36 figure 9. toggle bit algorithm........................................................ 37 dq2: toggle bit ii ................................................................... 37 reading toggle bits dq6/dq2 ............................................... 37 dq5: exceeded timing limits ................................................ 38 dq3: sector erase timer ....................................................... 38 dq1: write-to-buffer abort ..................................................... 38 table 15. write operation status ................................................... 38 absolute maximum ratings. . . . . . . . . . . . . . . . . 39 figure 10. maximum negative overshoot waveform ................... 39 figure 11. maximum positive overshoot waveform..................... 39 operating ranges . . . . . . . . . . . . . . . . . . . . . . . . . 39 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . 40 sram dc and operating characteristics. . . . . . 41 test conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . 42 figure 12. test setup.................................................................... 42 table 16. test specifications ......................................................... 42 key to switching waveforms. . . . . . . . . . . . . . . . 42 figure 13. input waveforms and measurement levels ................. 42 ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . 43 flash read-only operations ................................................. 43 figure 14. read operation timings ............................................... 43 figure 15. page read timings ...................................................... 44 hardware reset (reset#) .................................................... 45 figure 16. reset timings ............................................................... 45 flash erase and program operations .. .................................. 46 figure 17. program operation timings.......................................... 47 figure 18. accelerated program timing diagram.......................... 47 figure 19. chip/sector erase operation timings .......................... 48 figure 20. data# polling timings (during embedded algorithms). 49 figure 21. toggle bit timings (during embedded algorithms)...... 50 figure 22. dq2 vs. dq6................................................................. 50 temporary sector unprotect .................................................. 51 figure 23. temporary sector group unprotect timing diagram ... 51 figure 24. sector group protect and unprotect timing diagram .. 52 alternate ce# controlled erase and program operations ..... 53 figure 25. alternate ce# controlled write (erase/program) operation timings.......................................................................... 54 sram read cycle .................................................................. 55 figure 26. sram read cycle?address controlled...................... 55 figure 27. sram read cycle ........................................................ 56 sram write cycle .................................................................. 57 figure 28. sram write cycle?we# control ................................ 57 figure 29. sram write cycle?ce1#s control ............................. 58 figure 30. sram write cycle?ub#s and lb#s control ............... 59 erase and programming performance. . . . . . . . 60 flash latchup characteristics. . . . . . . . . . . . . . . 60 package pin capacitance. . . . . . . . . . . . . . . . . . . 61 data retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 sram data retention . . . . . . . . . . . . . . . . . . . . . . 62 figure 31. ce#1 controlled data retention mode......................... 62 figure 32. ce2s controlled data retention mode......................... 62 physical dimensions . . . . . . . . . . . . . . . . . . . . . . 63 tlb069?69-ball fine-pitch ball grid array (fbga) 8 x 10 mm package ................................................................ 64 revision summary . . . . . . . . . . . . . . . . . . . . . . . . 65
4 am41lv3204m june 10, 2003 preliminary product selector guide note: see ?ac characteristics? for full specifications. mcp block diagram family part number am41lv3204m flash memory sram speed option standard voltage range: v cc = 2.7?3.3 v 10 10 max access time (ns) 100 70 max. ce# access (ns) 100 70 max. page access time (t pacc )30 n/a oe# access (ns) 30 35 v ss /v ssq v cc s/v ccq reset# we# ce#f oe# ce1#s v ss v cc f ry/by# lb#s ub#s ciof wp#/acc ce2s sa cios 4 m bit static ram 32 m bit flash memory dq15/a-1 to dq0 dq15/a-1 to dq0 dq15/a-1 to dq0 a20 to a0 a20 to a0 a0 to a19 a ? 1 a17 to a0
june 10, 2003 am41lv3204m 5 preliminary flash memory block diagram input/output buffers x-decoder y-decoder chip enable output enable logic erase voltage generator pgm voltage generator timer v cc detector state control command register v cc v ss we# wp#/acc ce#f oe# stb stb dq15 ? dq0 sector switches reset#f data latch y-gating cell matrix address latch a20?a0
6 am41lv3204m june 10, 2003 preliminary connection diagrams special package handling instructions for fbga packages special handling is required for flash memory products in molded packages (bga). the package and/or data integrity may be compromised if the package body is exposed to temperatures about 150 c for prolonged periods of time. 69-ball fine-pitch bga top view, balls facing down a1 b1 e1 f1 k1 c2 d2 e2 f2 g2 h2 b3 c3 d3 e3 f3 g3 h3 j3 b4 c4 d4 e4 f4 g4 h4 j4 a5 b5 c5 d5 g5 h5 j5 k5 a6 b6 c6 d6 g6 h6 j6 k6 b7 c7 d7 e7 f7 g7 h7 j7 b8 c8 d8 e8 f8 g8 h8 j8 c9 d9 e9 f9 g9 h9 a10 e10 f10 k10 nc nc nc nc nc nc nc a3 a2 a1 a0 ce#f ce1#s a7 a6 a5 a4 v ss oe# dq0 dq8 lb# ub# a18 a17 dq1 dq9 dq10 dq2 nc wp#/acc reset# ry/by# dq3 v cc f dq11 nc we# ce2s a20 dq4 v cc s cios a8 a19 a9 a10 dq6 dq13 dq12 dq5 a11 a12 a13 a14 sa# dq15/a-1 dq7 dq14 a15 nc nc a16 ciof v ss nc nc nc nc sram only shared flash only
june 10, 2003 am41lv3204m 7 preliminary pin description a20?a0 = 21 address inputs dq14?dq0 = 15 data inputs/outputs dq15/a-1 = dq15 (data input/output, word mode), a-1 (25b address input, byte mode) ce#f = chip enable input (flash) ce1#s, ce2s= chip enable (sram) oe# = output enable input (flash) we# = write enable input (flash) wp#/acc = hardware write protect input/pro- gramming acceleration input (flash) reset#f = hardware reset pin input (flash) v cc f = flash 3.0 volt-only single power sup- ply (see product selector guide for speed options and voltage supply tolerances) v cc s = sram power supply v ss = device ground nc = pin not connected internally ub#s = upper byte control (sram) lb#s = lower byte control (sram) cios = i/o configuration (sram) cios = v ih = word mode (x16) cios = v il = byte mode (x8) sa = highest order address pin (sram) byte mode ciof = i/o configuration (flash) ciof = v ih = word mode (x16) ciof = v il = byte mode (x8) logic symbol 21 16 or 8 dq15?dq0 a20?a0 ce1#s oe# reset#f wp#/acc ub#s lb#s ce2s we# cios sa# (a-1) ry/by# ciof
8 am41lv3204m june 10, 2003 preliminary ordering information the order number (valid combination) is formed by the following: valid combinations valid combinations list configurations planned to be supported in vol- ume for this device. consult the local amd sales office to confirm availability of specific valid combinations and to check on newly re- leased combinations am41lv32x 4 m t 10 i t tape and reel t = 7 inches s = 13 inches temperature range i = industrial (?40 c to +85 c) speed option see product selector guide and valid combinations boot code sector architecture t=top sector b = bottom sector process technology m = 0.23 m mirrorbit sram device density 4= 4 mbits amd device number/description am41lv3204m stacked multi-chip package (mcp) flash memory and sram am29lv320m 32 megabit (4 m x 8-bit/2 m x 16-bit) flash memory and 4 mbit (512k x 8-bit/256 k x 16-bit) static ram valid combinations order number package marking am41lv3204mt10i t m410000095 am41lv3204mb10i m410000096
june 10, 2003 am41lv3204m 9 preliminary device bus operations this section describes the requirements and use of the device bus operations, which are initiated through the internal command register. the command register itself does not occupy any addressable memory loca- tion. the register is a latch used to store the com- mands, along with the address and data information needed to execute the command. the contents of the register serve as inputs to the internal state machine. the state machine outputs dictate the function of the device. table 1 lists the device bus operations, the in- puts and control levels they require, and the resulting output. the following subsections describe each of these operations in further detail.
10 am41lv3204m june 10, 2003 preliminary table 1. device bus operations?flash word mode, ciof = v ih , sram word mode, cios = v ih legend: l = logic low = v il , h = logic high = v ih , v id = 11.5?12.5 v, v hh = 9.0 0.5 v, x = don?t care, sa = sram address input, byte mode, sadd = flash sector address, a in = address in, d in = data in, d out = data out notes: 1. other operations except for those indicated in this column are inhibited. 2. do not apply ce#f = v il , ce1#s = v il and ce2s = v ih at the same time. 3. don?t care or open lb#s or ub#s. 4. if wp#/acc = v il , the boot sectors will be protected. if wp#/acc = v ih the boot sectors protection will be removed. if wp#/acc = v acc (9v), the program time will be reduced by 40%. 5. the sector protect and sector unprotect functions may also be implemented via programming equipment. see the ?? section. 6. if wp#/acc = v il , the two outermost boot sectors remain protected. if wp#/acc = v ih , the two outermost boot sector protection depends on whether they were last protected or unprotected using the method described in ??. if wp#/acc = v hh, all sectors will be unprotected. operation (notes 1, 2) ce#f ce1#s ce2s oe# we# sa addr. lb#s ub#s reset# wp#/acc (note 4) dq7? dq0 dq15? dq8 read from flash l hx lh x a in xx h l/h d out d out xl write to flash l hx hl x a in xx h (note 4)d in d in xl standby v cc 0.3 v hx xx x x x x v cc 0.3 v h high-z high-z xl output disable l l h hhxxlx h l/h high-z high-z hh x x x l flash hardware reset x hx x x x x x x l l/h high-z high-z xl sector protect (note 5) l hx hl x sadd, a6 = l, a1 = h, a0 = l xx v id l/h d in x xl sector unprotect (note 5) l hx hl x sadd, a6 = h, a1 = h, a0 = l xx v id (note 6) d in x xl temporary sector unprotect x hx xx x x x x v id (note 6) d in high-z xl read from sram h l h l h x a in ll hx d out d out hl high-zd out lh d out high-z write to sram h l h x l x a in ll hx d in d in hl high-zd in lh d in high-z
june 10, 2003 am41lv3204m 11 preliminary table 2. device bus operations ?flash word mode, ciof = v ih , sram word mode, cios = v il legend: l = logic low = v il , h = logic high = v ih , v id = 11.5?12.5 v, v hh = 9.0 0.5 v, x = don?t care, sa = sram address input, byte mode, sadd = flash sector address, a in = address in, d in = data in, d out = data out, dnu = do not use notes: 1. other operations except for those indicated in this column are inhibited. 2. do not apply ce#f = v il , ce1#s = v il and ce2s = v ih at the same time. 3. don?t care or open lb#s or ub#s. 4. if wp#/acc = v il , the boot sectors will be protected. if wp#/acc = v ih the boot sectors protection will be removed. if wp#/acc = v acc (9v), the program time will be reduced by 40%. 5. the sector protect and sector unprotect functions may also be implemented via programming equipment. see the ?? section. 6. if wp#/acc = v il , the two outermost boot sectors remain protected. if wp#/acc = v ih , the two outermost boot sector protection depends on whether they were last protected or unprotected using the method described in ??. if wp#/acc = v hh, all sectors will be unprotected. operation (notes 1, 2) ce#f ce1#s ce2s oe# we# sa addr. lb#s (note 3) ub#s (note 3) reset# wp#/acc (note 4) dq7? dq0 dq15? dq8 read from flash l hx lhx a in xx h l/hd out d out xl write to flash l hx hlx a in x x h (note 3) d in d in xl standby v cc 0.3 v hx xxx x x x v cc 0.3 v h high-z high-z xl output disable l l h h h sa x dnu dnu h l/h high-z high-z flash hardware reset x hx x x x x x x l l/h high-z high-z xl sector protect (note 5) l hx hlx sadd, a6 = l, a1 = h, a0 = l xxv id l/h d in x xl sector unprotect (note 5) l hx hlx sadd, a6 = h, a1 = h, a0 = l xxv id (note 6) d in x xl temporary sector unprotect x hx xxx a in xxv id (note 6) d in high-z xl read from sram h l h l h sa a in xx h xd out high-z write to sram h l h x l sa a in xx h xd in high-z
12 am41lv3204m june 10, 2003 preliminary table 3. device bus operations?flash byte mode, ciof = v il ; sram word mode, cios = v cc legend: l = logic low = v il , h = logic high = v ih , v id = 11.5?12.5 v, v hh = 9.0 0.5 v, x = don?t care, sa = sram address input, byte mode, sadd = flash sector address, a in = address in (for flash byte mode, dq15 = a-1), d in = data in, d out = data out notes: 1. other operations except for those indicated in this column are inhibited. 2. do not apply ce#f = v il , ce1#s = v il and ce2s = v ih at the same time. 3. don?t care or open lb#s or ub#s. 4. if wp#/acc = v il , the boot sectors will be protected. if wp#/acc = v ih the boot sectors protection will be removed. if wp#/acc = v acc (9v), the program time will be reduced by 40%. 5. the sector protect and sector unprotect functions may also be implemented via programming equipment. see the ?? section. 6. if wp#/acc = v il , the two outermost boot sectors remain protected. if wp#/acc = v ih , the two outermost boot sector protection depends on whether they were last protected or unprotected using the method described in ??. if wp#/acc = v hh, all sectors will be unprotected. operation (notes 1, 2) ce#f ce1#s ce2s oe# we# sa addr. lb#s (note 3) ub#s (note 3) reset# wp#/acc (note 4) dq7? dq0 dq15? dq8 read from flash l hx lhx a in xxhl/hd out high-z xl write to flash l hx hlx a in xxh (note 3) d in high-z xl standby v cc 0.3 v hx xxx x x x v cc 0.3 v h high-z high-z xl output disable l l h h h x x lx h l/h high-z high-z xl flash hardware reset x hx x x x x x x l l/h high-z high-z xl sector protect (note 5) l hx hlx sadd, a6 = l, a1 = h, a0 = l xxv id l/h d in x xl sector unprotect (note 5) l hx hlx sadd, a6 = l, a1 = h, a0 = l xxv id (note 6) d in x xl temporary sector unprotect x hx xxx a in xxv id (note 6) d in high-z xl read from sram hlhlhxa in ll hx d out d out h l high-z d out lh d out high-z write to sram h l h x l x a in ll hx d in d in h l high-z d in lh d in high-z
june 10, 2003 am41lv3204m 13 preliminary table 4. device bus operations?flash byte mode, ciof = v il ; sram byte mode, cios = v ss legend: l = logic low = v il , h = logic high = v ih , v id = 11.5?12.5 v, v hh = 9.0 0.5 v, x = don?t care, sa = sram address input, byte mode, sadd = flash sector address, a in = address in (for flash byte mode, dq15 = a-1), d in = data in, d out = data out, dnu = do not use notes: 1. other operations except for those indicated in this column are inhibited. 2. do not apply ce#f = v il , ce1#s = v il and ce2s = v ih at the same time. 3. don?t care or open lb#s or ub#s. 4. if wp#/acc = v il , the boot sectors will be protected. if wp#/acc = v ih the boot sectors protection will be removed. if wp#/acc = v acc (9v), the program time will be reduced by 40%. 5. the sector protect and sector unprotect functions may also be implemented via programming equipment. see the ??. 6. if wp#/acc = v il , the two outermost boot sectors remain protected. if wp#/acc = v ih , the two outermost boot sector protection depends on whether they were last protected or unprotected using the method described in ??. if wp#/acc = v hh, all sectors will be unprotected. operation (notes 1, 2) ce#f ce1#s ce2s oe# we# sa addr. lb#s (note 3) ub#s (note 3) reset# wp#/acc (note 4) dq7? dq0 dq15? dq8 read from flash l hx lh x a in xxhl/hd out high-z xl write to flash l hx hl x a in xxh (note 3) d in high-z xl standby v cc 0.3 v hx xxxxxx v cc 0.3 v h high-z high-z xl output disable h l h h h sa x dnu dnu h l/h high-z high-z flash hardware reset x hx x x x x x x l l/h high-z high-z xl sector protect (note 5) l hx hl x sadd, a6 = l, a1 = h, a0 = l xxv id l/h d in x xl sector unprotect (note 5) l hx hl x sadd, a6 = l, a1 = h, a0 = l xxv id (note 6) d in x xl temporary sector unprotect x hx xx x a in xxv id (note 6) d in high-z xl read from sram h l h l h sa a in xxh xd out high-z write to sram h l h x l sa a in xxh xd in high-z
14 am41lv3204m june 10, 2003 preliminary requirements for reading array data to read array data from the outputs, the system must drive the ce# and oe# pins to v il . ce# is the power control and selects the device. oe# is the output con- trol and gates array data to the output pins. we# should remain at v ih . the ciof pin determines whether the device outputs array data in words or bytes. the internal state machine is set for reading array data upon device power-up, or after a hardware reset. this ensures that no spurious alteration of the memory content occurs during the power transition. no com- mand is necessary in this mode to obtain array data. standard microprocessor read cycles that assert valid addresses on the device address inputs produce valid data on the device data outputs. the device remains enabled for read access until the command register contents are altered. see ?reading array data? for more information. refer to the ac flash read-only operations table for timing specifications and to figure 14 for the timing diagram. refer to the dc characteristics table for the active current specification on reading array data. page mode read the device is capable of fast page mode read and is compatible with the page mode mask rom read oper- ation. this mode provides faster read access speed for random locations within a page. the page size of the device is 4 words/8-bytes. the appropriate page is selected by the higher address bits a(max)?a2. ad- dress bits a1?a0 determine the specific word within a page. this is an asynchronous operation; the micro- processor supplies the specific word location. the random or initial page access is equal to t acc or t ce and subsequent page read accesses (as long as the locations specified by the microprocessor falls within that page) is equivalent to t pacc . when ce#f is deasserted and reasserted for a subsequent access, the access time is t acc or t ce . fast page mode ac- cesses are obtained by keeping the ?read-page ad- dresses? constant and changing the ?intra-read page? addresses. writing commands/command sequences to write a command or command sequence (which in- cludes programming data to the device and erasing sectors of memory), the system must drive we# and ce# to v il , and oe# to v ih . the device features an unlock bypass mode to facil- itate faster programming. once the device enters the unlock bypass mode, only two write cycles are re- quired to program a word or byte, instead of four. the ?word program command sequence? section has de- tails on programming data to the device using both standard and unlock bypass command sequences. an erase operation can erase one sector, multiple sec- tors, or the entire device. tables 3 and 2 indicates the address space that each sector occupies. refer to the dc characteristics table for the active current specification for the write mode. the ac char- acteristics section contains timing specification tables and timing diagrams for write operations. write buffer write buffer programming allows the system to write a maximum of 16 words/32-bytes in one programming operation. this results in faster effective programming time than the standard programming algorithms. see ?write buffer? for more information. accelerated program operation the device offers accelerated program operations through the acc function. this is one of two functions provided by the wp#/acc pin. this function is prima- rily intended to allow faster manufacturing throughput at the factory. if the system asserts v hh on this pin, the device auto- matically enters the aforementioned unlock bypass mode, temporarily unprotects any protected sectors, and uses the higher voltage on the pin to reduce the time required for program operations. the system would use a two-cycle program command sequence as required by the unlock bypass mode. removing v hh from the wp#/acc pin returns the device to nor- mal operation. note that the wp#/acc pin must not be at v hh for operations other than accelerated pro- gramming, or device damage may result. in addition, no external pullup is necessary since the wp#/acc pin has internal pullup to v cc . autoselect functions if the system writes the autoselect command se- quence, the device enters the autoselect mode. the system can then read autoselect codes from the inter- nal register (which is separate from the memory array) on dq7?dq0. standard read cycle timings apply in this mode. refer to the autoselect mode and autose- lect command sequence sections for more informa- tion. standby mode when the system is not reading or writing to the de- vice, it can place the device in the standby mode. in this mode, current consumption is greatly reduced, and the outputs are placed in the high impedance state, independent of the oe# input. the device enters the cmos standby mode when the ce#f and reset# pins are both held at v cc 0.3 v.
june 10, 2003 am41lv3204m 15 preliminary (note that this is a more restricted voltage range than v ih .) if ce#f and reset# are held at v ih , but not within v cc 0.3 v, the device will be in the standby mode, but the standby current will be greater. the de- vice requires standard access time (t ce ) for read ac- cess when the device is in either of these standby modes, before it is ready to read data. if the device is deselected during erasure or program- ming, the device draws active current until the operation is completed. refer to the dc characteristics table for the standby current specification. automatic sleep mode the automatic sleep mode minimizes flash device en- ergy consumption. the device automatically enables this mode when addresses remain stable for t acc + 30 ns. the automatic sleep mode is independent of the ce#, we#, and oe# control signals. standard ad- dress access timings provide new data when ad- dresses are changed. while in sleep mode, output data is latched and always available to the system. refer to the dc characteristics table for the automatic sleep mode current specification. reset#: hardware reset pin the reset# pin provides a hardware method of re- setting the device to reading array data. when the re- set# pin is driven low for at least a period of t rp , the device immediately terminates any operation in progress, tristates all output pins, and ignores all read/write commands for the duration of the reset# pulse. the device also resets the internal state ma- chine to reading array data. the operation that was in- terrupted should be reinitiated once the device is ready to accept another command sequence, to en- sure data integrity. current is reduced for the duration of the reset# pulse. when reset# is held at v ss 0.3 v, the device draws cmos standby current (i cc4 ). if reset# is held at v il but not within v ss 0.3 v, the standby current will be greater. the reset# pin may be tied to the system reset cir- cuitry. a system reset would thus also reset the flash memory, enabling the system to read the boot-up firm- ware from the flash memory. refer to the ac characteristics tables for reset# pa- rameters and to figure 16 for the timing diagram. output disable mode when the oe# input is at v ih , output from the device is disabled. the output pins are placed in the high impedance state.
16 am41lv3204m june 10, 2003 preliminary table 5. am29lv320m top boot sector architecture sector sector address a20?a12 sector size (kbytes/kwords) (x8) address range (x16) address range sa0 000000xxx 64/32 000000h?00ffffh 00000h?07fffh sa1 000001xxx 64/32 010000h?01ffffh 08000h?0ffffh sa2 000010xxx 64/32 020000h?02ffffh 10000h?17fffh sa3 000011xxx 64/32 030000h?03ffffh 18000h?1ffffh sa4 000100xxx 64/32 040000h?04ffffh 20000h?27fffh sa5 000101xxx 64/32 050000h?05ffffh 28000h?2ffffh sa6 000110xxx 64/32 060000h?06ffffh 30000h?37fffh sa7 000111xxx 64/32 070000h?07ffffh 38000h?3ffffh sa8 001000xxx 64/32 080000h?08ffffh 40000h?47fffh sa9 001001xxx 64/32 090000h?09ffffh 48000h?4ffffh sa10 001010xxx 64/32 0a0000h?0affffh 50000h?57fffh sa11 001011xxx 64/32 0b0000h?0bffffh 58000h?5ffffh sa12 001100xxx 64/32 0c0000h?0cffffh 60000h?67fffh sa13 001101xxx 64/32 0d0000h?0dffffh 68000h?6ffffh sa14 001101xxx 64/32 0e0000h?0effffh 70000h?77fffh sa15 001111xxx 64/32 0f 0000h?0fffffh 78000h?7ffffh sa16 010000xxx 64/32 100000h?00ffffh 80000h?87fffh sa17 010001xxx 64/32 110000h?11ffffh 88000h?8ffffh sa18 010010xxx 64/32 120000h?12ffffh 90000h?97fffh sa19 010011xxx 64/32 130000h?13ffffh 98000h?9ffffh sa20 010100xxx 64/32 140000h?14ffffh a0000h?a7fffh sa21 010101xxx 64/32 150000h?15ffffh a8000h?affffh sa22 010110xxx 64/32 160000h?16ffffh b0000h?b7fffh sa23 010111xxx 64/32 170000h?17ffffh b8000h?bffffh sa24 011000xxx 64/32 180000h?18ffffh c0000h?c7fffh sa25 011001xxx 64/32 190000h?19ffffh c8000h?cffffh sa26 011010xxx 64/32 1a0000h?1affffh d0000h?d7fffh sa27 011011xxx 64/32 1b0000h?1bffffh d8000h?dffffh sa28 011000xxx 64/32 1c0000h?1cffffh e0000h?e7fffh sa29 011101xxx 64/32 1d0000h?1dffffh e8000h?effffh sa30 011110xxx 64/32 1e0000h?1effffh f0000h?f7fffh sa31 011111xxx 64/32 1f0000h?1fffffh f8000h?fffffh sa32 100000xxx 64/32 200000h?20ffffh f9000h?107fffh sa33 100001xxx 64/32 210000h?21ffffh 108000h?10ffffh sa34 100010xxx 64/32 220000h?22ffffh 110000h?117fffh sa35 101011xxx 64/32 230000h?23ffffh 118000h?11ffffh sa36 100100xxx 64/32 240000h?24ffffh 120000h?127fffh sa37 100101xxx 64/32 250000h?25ffffh 128000h?12ffffh sa38 100110xxx 64/32 260000h?26ffffh 130000h?137fffh sa39 100111xxx 64/32 270000h?27ffffh 138000h?13ffffh sa40 101000xxx 64/32 280000h?28ffffh 140000h?147fffh sa41 101001xxx 64/32 290000h?29ffffh 148000h?14ffffh sa42 101010xxx 64/32 2a0000h?2affffh 150000h?157fffh sa43 101011xxx 64/32 2b0000h?2bffffh 158000h?15ffffh sa44 101100xxx 64/32 2c0000h?2cffffh 160000h?167fffh sa45 101101xxx 64/32 2d0000h?2dffffh 168000h?16ffffh sa46 101110xxx 64/32 2e0000h?2effffh 170000h?177fffh sa47 101111xxx 64/32 2f 0000h?2fffffh 178000h?17ffffh sa48 110000xxx 64/32 300000h?30ffffh 180000h?187fffh sa49 110001xxx 64/32 310000h?31ffffh 188000h?18ffffh sa50 110010xxx 64/32 320000h?32ffffh 190000h?197fffh sa51 110011xxx 64/32 330000h?33ffffh 198000h?19ffffh sa52 100100xxx 64/32 340000h?34ffffh 1a0000h?1a7fffh
june 10, 2003 am41lv3204m 17 preliminary sa53 110101xxx 64/32 350000h?35ffffh 1a8000h?1affffh sa54 110110xxx 64/32 360000h?36ffffh 1b0000h?1b7fffh sa55 110111xxx 64/32 370000h?37ffffh 1b8000h?1bffffh sa56 111000xxx 64/32 380000h?38ffffh 1c0000h?1c7fffh sa57 111001xxx 64/32 390000h?39ffffh 1c8000h?1cffffh sa58 111010xxx 64/32 3a0000h?3affffh 1d0000h?1d7fffh sa59 111011xxx 64/32 3b0000h?3bffffh 1d8000h?1dffffh sa60 111100xxx 64/32 3c0000h?3cffffh 1e0000h?1e7fffh sa61 111101xxx 64/32 3d0000h?3dffffh 1e8000h?1effffh sa62 111110xxx 64/32 3e0000h?3effffh 1f0000h?1f7fffh sa63 111111000 8/4 3f0000h?3f1fffh 1f8000h?1f8fffh sa64 111111001 8/4 3f2000h?3f3fffh 1f9000h?1f9fffh sa65 111111010 8/4 3f4000h?3f5fffh 1fa000h?1fafffh sa66 111111011 8/4 3f 6000h?3f7fffh 1fb000h?1fbfffh sa67 111111100 8/4 3f 8000h?3f9fffh 1fc000h?1fcfffh sa68 111111101 8/4 3fa 000h?3fbfffh 1fd000h?1fdfffh sa69 111111110 8/4 3fc 000h?3fdfffh 1fe000h?1fefffh sa70 111111111 8/4 3fe 000h?3fffffh 1ff000h?1fffffh table 5. am29lv320m top boot sector architecture sector sector address a20?a12 sector size (kbytes/kwords) (x8) address range (x16) address range
18 am41lv3204m june 10, 2003 preliminary sector group protection and unprotection the hardware sector group protection feature disables both program and erase operations in any sector group. in this device, a sector group consists of four adjacent sectors that are protected or unprotected at the same time (see tables 4 and 6 ). the hardware sector group unprotection feature re-enables both pro- gram and erase operations in previously protected sector groups. sector group protection/unprotection can be implemented via two methods. sector protection/unprotection requires v id on the re- set# pin only, and can be implemented either in-sys- tem or via programming equipment. figure 2 shows the algorithms and figure 24 shows the timing dia- gram. this method uses standard microprocessor bus cycle timing. for sector group unprotect, all unpro- tected sector groups must first be protected prior to the first sector group unprotect write cycle. the device is shipped with all sector groups unpro- tected. amd offers the option of programming and protecting sector groups at its factory prior to shipping the device through amd?s expressflash? service. contact an amd representative for details. it is possible to determine whether a sector group is protected or unprotected. see the autoselect mode section for details. table 6. am29lv320mt top boot sector protection write protect (wp#) the write protect function provides a hardware method of protecting the top two or bottom two sectors without using v id . wp# is one of two functions pro- vided by the wp#/acc input. if the system asserts v il on the wp#/acc pin, the de- vice disables program and erase functions in the first or last sector independently of whether those sectors were protected or unprotected using the method de- scribed in ?sector group protection and unprotection?. note that if wp#/acc is at v il when the device is in sector a20?a12 sector/ sector block size sa0-sa3 0000xxxxxh 256 (4x64) kbytes sa4-sa7 0001xxxxxh 256 (4x64) kbytes sa8-sa11 0010xxxxxh 256 (4x64) kbytes sa12-sa15 0011xxxxxh 256 (4x64) kbytes sa16-sa19 0100xxxxxh 256 (4x64) kbytes sa20-sa23 0101xxxxxh 256 (4x64) kbytes sa24-sa27 0110xxxxxh 256 (4x64) kbytes sa28-sa31 0111xxxxxh 256 (4x64) kbytes sa32?sa35 1000xxxxxh, 256 (4x64) kbytes sa36?sa39 1001xxxxxh 256 (4x64) kbytes sa40?sa43 1010xxxxxh 256 (4x64) kbytes sa44?sa47 1011xxxxxh 256 (4x64) kbytes sa48?sa51 1100xxxxxh 256 (4x64) kbytes sa52-sa55 1101xxxxxh 256 (4x64) kbytes sa56-sa59 1110xxxxxh 256 (4x64) kbytes sa60-sa62 111100xxxh 111101xxxh 111110xxxh 192 (3x64) kbytes sa63 11111 1000h 8 kbytes sa64 11111 1001h 8 kbytes sa65 11111 1010h 8 kbytes sa66 111111011h 8 kbytes sa67 111111100h 8 kbytes sa68 111111101h 8 kbytes sa69 111111110h 8 kbytes sa70 111111111h 8 kbytes table 7. am29lv320mb bottom boot sector protection sector a20?a12 sector/ sector block size sa0 000000000h 8 kbytes sa1 000000001h 8 kbytes sa2 000000010h 8 kbytes sa3 000000011h 8 kbytes sa4 000000100h 8 kbytes sa5 000000101h 8 kbytes sa6 000000110h 8 kbytes sa7 000000111h 8 kbytes sa8?sa10 000001xxxh, 000010xxxh, 000011xxxh, 192 (3x64) kbytes sa11?sa14 0001xxxxxh 256 (4x64) kbytes sa15?sa18 0010xxxxxh 256 (4x64) kbytes sa19?sa22 0011xxxxxh 256 (4x64) kbytes sa23?sa26 0100xxxxxh 256 (4x64) kbytes sa27-sa30 0101xxxxxh 256 (4x64) kbytes sa31-sa34 0110xxxxxh 256 (4x64) kbytes sa35-sa38 0111xxxxxh 256 (4x64) kbytes sa39-sa42 1000xxxxxh 256 (4x64) kbytes sa43-sa46 1001xxxxxh 256 (4x64) kbytes sa47-sa50 1010xxxxxh 256 (4x64) kbytes sa51-sa54 1011xxxxxh 256 (4x64) kbytes sa55?sa58 1100xxxxxh 256 (4x64) kbytes sa59?sa62 1101xxxxxh 256 (4x64) kbytes sa63?sa66 1110xxxxxh 256 (4x64) kbytes sa67?sa70 1111x xxxxh 256 (4x64) kbytes sector a20?a12 sector/ sector block size
june 10, 2003 am41lv3204m 19 preliminary the standby mode, the maximum input load current is increased. see the table in ?dc characteristics?. if the system asserts v ih on the wp#/acc pin, the de- vice reverts to whether the top or bottom two sectors were previously set to be protected or unprotected using the method described in ?sector group protec- tion and unprotection?. note: no external pullup is necessary since the wp#/acc pin has internal pullup to v cc temporary sector group unprotect ( note: in this device, a sector group consists of four adjacent sectors that are protected or unprotected at the same time (see ta ble 6 ). this feature allows temporary unprotection of previ- ously protected sector groups to change data in-sys- tem. the sector group unprotect mode is activated by setting the reset# pin to vid . during this mode, for- merly protected sector groups can be programmed or erased by selecting the sector group addresses. once v id is removed from the reset# pin, all the previ- ously protected sector groups are protected again. figure 1 shows the algorithm, and figure 23 shows the timing diagrams, for this feature. figure 1. temporary sector group unprotect operation start perform erase or program operations reset# = v ih temporary sector group unprotect completed (note 2) reset# = v id (note 1) notes: 1. all protected sector groups unprotected (if wp# = v il , the first or last sector will remain protected). 2. all previously protected sector groups are protected once again.
20 am41lv3204m june 10, 2003 preliminary figure 2. in-system sector group protect/unprotect algorithms sector group protect: write 60h to sector group address with a6?a0 = 0xx0010 set up sector group address wait 150 s verify sector group protect: write 40h to sector group address with a6?a0 = 0xx0010 read from sector group address with a6?a0 = 0xx0010 start plscnt = 1 reset# = v id wait 1 s first write cycle = 60h? data = 01h? remove v id from reset# write reset command sector group protect complete yes yes no plscnt = 25? yes device failed increment plscnt temporary sector group unprotect mode no sector group unprotect: write 60h to sector group address with a6?a0 = 1xx0010 set up first sector group address wait 15 ms verify sector group unprotect: write 40h to sector group address with a6?a0 = 1xx0010 read from sector group address with a6?a0 = 1xx0010 start plscnt = 1 reset# = v id wait 1 s data = 00h? last sector group verified? remove v id from reset# write reset command sector group unprotect complete yes no plscnt = 1000? yes device failed increment plscnt temporary sector group unprotect mode no all sector groups protected? yes protect all sector groups: the indicated portion of the sector group protect algorithm must be performed for all unprotected sector groups prior to issuing the first sector group unprotect address set up next sector group address no yes no yes no no yes no sector group protect algorithm sector group unprotect algorithm first write cycle = 60h? protect another sector group? reset plscnt = 1
june 10, 2003 am41lv3204m 21 preliminary secsi (secured silicon) sector flash memory region the secsi (secured silicon) sector feature provides a flash memory region that enables permanent part identification through an electronic serial number (esn). the secsi sector is 128 words in length, and uses a secsi sector indicator bit (dq7) to indicate whether or not the secsi sector is locked when shipped from the factory. this bit is permanently set at the factory and cannot be changed, which prevents cloning of a factory locked part. this ensures the secu- rity of the esn once the product is shipped to the field. amd offers the device with the secsi sector either factory locked or customer lockable. the fac- tory-locked version is always protected when shipped from the factory, and has the secsi (secured silicon) sector indicator bit permanently set to a ?1.? the cus- tomer-lockable version is shipped with the secsi sec- tor unprotected, allowing customers to program the sector after receiving the device. the customer-lock- able version also has the secsi sector indicator bit permanently set to a ?0.? thus, the secsi sector indi- cator bit prevents customer-lockable devices from being used to replace devices that are factory locked. the secsi sector address space in this device is allo- cated as follows: the system accesses the secsi sector through a command sequence (see ?enter secsi sector/exit secsi sector command sequence?). after the system has written the enter secsi sector command se- quence, it may read the secsi sector by using the ad- dresses normally occupied by the first sector (sa0). this mode of operation continues until the system is- sues the exit secsi sector command sequence, or until power is removed from the device. on power-up, or following a hardware reset, the device reverts to sending commands to sector sa0. factory locked: secsi s ector programmed and protected at the factory in devices with an esn, the secsi sector is protected when the device is shipped from the factory. the secsi sector cannot be modified in any way. see ta b l e 5 for secsi sector addressing. customers may opt to have their code programmed by amd through the amd expressflash service. the de- vices are then shipped from amd?s factory with the secsi sector permanently locked. contact an amd representative for details on using amd?s express- flash service. customer lockable: secsi sector not programmed or protect ed at the factory as an alternative to the factory-locked version, the de- vice may be ordered such that the customer may pro- gram and protect the 128-word/256-bytes secsi sector. the system may program the secsi sector using the write-buffer, accelerated and/or unlock bypass meth- ods, in addition to the standard programming com- mand sequence. see command definitions . programming and protecting the secsi sector must be used with caution since, once protected, there is no procedure available for unprotecting the secsi sector area and none of the bits in the secsi sector memory space can be modified in any way. the secsi sector area can be protected using one of the following procedures: write the three-cycle enter secsi sector region command sequence, and then follow the in-system sector protect algorithm as shown in figure 2, ex- cept that reset# may be at either v ih or v id . this allows in-system protection of the secsi sector without raising any device pin to a high voltage. note that this method is only applicable to the secsi sector. to verify the protect/unprotect status of the secsi sector, follow the algorithm shown in figure 3. once the secsi sector is programmed, locked and verified, the system must write the exit secsi sector region command sequence to return to reading and writing within the remainder of the array. table 8. secsi sector contents secsi sector address range standard factory locked expressflash factory locked customer lockable x16 000000h? 000007h esn esn or determined by customer determined by customer 000008h? 00007fh unavailable determined by customer
22 am41lv3204m june 10, 2003 preliminary figure 3. secsi sector protect verify hardware data protection the command sequence requirement of unlock cycles for programming or erasing provides data protection against inadvertent writes (refer to tables 10 and 13 for command definitions). in addition, the following hardware data protection measures prevent accidental erasure or programming, which might otherwise be caused by spurious system level signals during v cc power-up and power-down transitions, or from system noise. low v cc write inhibit when v cc is less than v lko , the device does not ac- cept any write cycles. this protects data during v cc power-up and power-down. the command register and all internal program/erase circuits are disabled, and the device resets to the read mode. subsequent writes are ignored until v cc is greater than v lko . the system must provide the proper signals to the control pins to prevent unintentional writes when v cc is greater than v lko . write pulse ?glitch? protection noise pulses of less than 5 ns (typical) on oe#, ce#f or we# do not initiate a write cycle. logical inhibit write cycles are inhibited by holding any one of oe# = v il , ce# = v ih or we# = v ih . to initiate a write cycle, ce# and we# must be a logical zero while oe# is a logical one. power-up write inhibit if we# = ce#f = v il and oe# = v ih during power up, the device does not accept commands on the rising edge of we#. the internal state machine is automati- cally reset to the read mode on power-up. common flash memory interface (cfi) the common flash interface (cfi) specification out- lines device and host system software interrogation handshake, which allows specific vendor-specified software algorithms to be used for entire families of devices. software support can then be device-inde- pendent, jedec id-independent, and forward- and backward-compatible for the specified flash device families. flash vendors can standardize their existing interfaces for long-term compatibility. this device enters the cfi query mode when the sys- tem writes the cfi query command, 98h, to address 55h, any time the device is ready to read array data. the system can read cfi information at the addresses given in tables 6 ? 9 . to terminate reading cfi data, the system must write the reset command. the system can also write the cfi query command when the device is in the autoselect mode. the device enters the cfi query mode, and the system can read cfi data at the addresses given in tables 6 ? 9 . the system must write the reset command to return the de- vice to reading array data. for further information, please refer to the cfi specifi- cation and cfi publication 100, available via the world wide web at http://www.amd.com/flash/cfi. al- ternatively, contact an amd representative for copies of these documents. write 60h to any address write 40h to secsi sector address with a6 = 0, a1 = 1, a0 = 0 start reset# = v ih or v id wait 1 s read from secsi sector address with a6 = 0, a1 = 1, a0 = 0 if data = 00h, secsi sector is unprotected. if data = 01h, secsi sector is protected. remove v ih or v id from reset# write reset command secsi sector protect verify complete
june 10, 2003 am41lv3204m 23 preliminary table 9. cfi query id entification string table 10. system interface string addresses (x16) addresses (x8) data description 10h 11h 12h 20h 22h 24h 0051h 0052h 0059h query unique ascii string ?qry? 13h 14h 26h 28h 0002h 0000h primary oem command set 15h 16h 2ah 2ch 0040h 0000h address for primary extended table 17h 18h 2eh 30h 0000h 0000h alternate oem command set (00h = none exists) 19h 1ah 32h 34h 0000h 0000h address for alternate oem extended table (00h = none exists) addresses (x16) addresses (x8) data description 1bh 36h 0027h v cc min. (write/erase) d7?d4: volt, d3?d0: 100 millivolt 1ch 38h 0036h v cc max. (write/erase) d7?d4: volt, d3?d0: 100 millivolt 1dh 3ah 0000h v pp min. voltage (00h = no v pp pin present) 1eh 3ch 0000h v pp max. voltage (00h = no v pp pin present) 1fh 3eh 0007h typical timeout per single word write 2 n s 20h 40h 0007h typical timeout for min. size buffer write 2 n s (00h = not supported) 21h 42h 000ah typical timeout per individual block erase 2 n ms 22h 44h 0000h typical timeout for full chip erase 2 n ms (00h = not supported) 23h 46h 0001h max. timeout for word write 2 n times typical 24h 48h 0005h max. timeout for buffer write 2 n times typical 25h 4ah 0004h max. timeout per individual block erase 2 n times typical 26h 4ch 0000h max. timeout for full chip erase 2 n times typical (00h = not supported)
24 am41lv3204m june 10, 2003 preliminary table 11. device geometry definition addresses (x16) addresses (x8) data description 27h 4eh 0016h device size = 2 n byte 28h 29h 50h 52h 0002h 0000h flash device interface description (refer to cfi publication 100) 2ah 2bh 54h 56h 0005h 0000h max. number of byte in multi-byte write = 2 n (00h = not supported) 2ch 58h 0002h number of erase block regions within device (01h = uniform device, 02h = boot device) 2dh 2eh 2fh 30h 5ah 5ch 5eh 60h 007fh 0000h 0020h 0000h erase block region 1 information (refer to the cfi specification or cfi publication 100) 31h 32h 33h 34h 62h 64h 66h 68h 003eh 0000h 0000h 0001h erase block region 2 information (refer to cfi publication 100) 35h 36h 37h 38h 6ah 6ch 6eh 70h 0000h 0000h 0000h 0000h erase block region 3 information (refer to cfi publication 100) 39h 3ah 3bh 3ch 72h 74h 76h 78h 0000h 0000h 0000h 0000h erase block region 4 information (refer to cfi publication 100)
june 10, 2003 am41lv3204m 25 preliminary table 12. primary vendor-specific extended query command definitions writing specific address and data commands or se- quences into the command register initiates device op- erations. tables 10 and 13 define the valid register command sequences. writing incorrect address and data values or writing them in the improper se- quence may place the device in an unknown state. a reset command is then required to return the device to reading array data. all addresses are latched on the falling edge of we# or ce#f, whichever happens later. all data is latched on the rising edge of we# or ce#f, whichever hap- pens first. refer to the ac characteristics section for timing diagrams. reading array data the device is automatically set to reading array data after device power-up. no commands are required to retrieve data. the device is ready to read array data after completing an embedded program or embedded erase algorithm. after the device accepts an erase suspend command, the device enters the erase-suspend-read mode, after addresses (x16) addresses (x8) data description 40h 41h 42h 80h 82h 84h 0050h 0052h 0049h query-unique ascii string ?pri? 43h 86h 0031h major version number, ascii 44h 88h 0033h minor version number, ascii 45h 8ah 0008h address sensitive unlock (bits 1-0) 0 = required, 1 = not required process technology (bits 7-2) 0010b = 0.23 m mirrorbit 46h 8ch 0002h erase suspend 0 = not supported, 1 = to read only, 2 = to read & write 47h 8eh 0001h sector protect 0 = not supported, x = number of sectors in per group 48h 90h 0001h sector temporary unprotect 00 = not supported, 01 = supported 49h 92h 0004h sector protect/unprotect scheme 04 = 29lv800 mode 4ah 94h 0000h simultaneous operation 00 = not supported, x = number of sectors in bank 4bh 96h 0000h burst mode type 00 = not supported, 01 = supported 4ch 98h 0001h page mode type 00 = not supported, 01 = 4 word page, 02 = 8 word page 4dh 9ah 00b5h acc (acceleration) supply minimum 00h = not supported, d7-d4: volt, d3-d0: 100 mv 4eh 9ch 00c5h acc (acceleration) supply maximum 00h = not supported, d7-d4: volt, d3-d0: 100 mv 4fh 9eh 0003h top/bottom boot sector flag 00h = uniform device without wp# protect, 02h = bottom boot device, 03h = top boot device, 04h = uniform sectors bottom wp# protect, 05h = uniform sectors top wp# protect 50h a0h 0001h program suspend 00h = not supported, 01h = supported
26 am41lv3204m june 10, 2003 preliminary which the system can read data from any non-erase-suspended sector. after completing a pro- gramming operation in the erase suspend mode, the system may once again read array data with the same exception. see the erase suspend/erase resume commands section for more information. the system must issue the reset command to return the device to the read (or erase-suspend-read) mode if dq5 goes high during an active program or erase operation, or if the device is in the autoselect mode. see the next section, reset command , for more infor- mation. see also requirements for reading array data in the device bus operations section for more information. the flash read-only operations table provides the read parameters, and figure 14 shows the timing dia- gram. reset command writing the reset command resets the device to the read or erase-suspend-read mode. address bits are don?t cares for this command. the reset command may be written between the se- quence cycles in an erase command sequence before erasing begins. this resets the device to the read mode. once erasure begins, however, the device ig- nores reset commands until the operation is complete. the reset command may be written between the sequence cycles in a program command sequence before programming begins. this resets the device to the read mode. if the program command sequence is written while the device is in the erase suspend mode, writing the reset command returns the device to the erase-suspend-read mode. once programming be- gins, however, the device ignores reset commands until the operation is complete. the reset command may be written between the se- quence cycles in an autoselect command sequence. once in the autoselect mode, the reset command must be written to return to the read mode. if the de- vice entered the autoselect mode while in the erase suspend mode, writing the reset command returns the device to the erase-suspend-read mode. if dq5 goes high during a program or erase operation, writing the reset command returns the device to the read mode (or erase-suspend-read mode if the device was in erase suspend). note that if dq1 goes high during a write buffer pro- gramming operation, the system must write the write-to-buffer-abort reset command sequence to reset the device for the next operation. autoselect command sequence the autoselect command sequence allows the host system to read several identifier codes at specific ad- dresses: note: the device id is read over three cycles. sa = sector address. tables 10 and 13 show the address and data require- ments. this method is an alternative to that shown in ta b l e 3 , which is intended for prom programmers and requires v id on address pin a9. the autoselect command sequence may be written to an address that is either in the read or erase-suspend-read mode. the autoselect command may not be written while the de- vice is actively programming or erasing. the autoselect command sequence is initiated by first writing two unlock cycles. this is followed by a third write cycle that contains the autoselect command. the device then enters the autoselect mode. the system may read at any address any number of times without initiating another autoselect command sequence. the system must write the reset command to return to the read mode (or erase-suspend-read mode if the de- vice was previously in erase suspend). enter secsi sector/exit secsi sector command sequence the secsi sector region provides a secured data area containing an 8-word/16-byte random electronic serial number (esn). the system can access the secsi sector region by issuing the three-cycle enter secsi sector command sequence. the device continues to access the secsi sector region until the system is- sues the four-cycle exit secsi sector command se- quence. the exit secsi sector command sequence returns the device to normal operation. tables 10 and 13 show the address and data requirements for both command sequences. see also ?secsi (secured sili- con) sector flash memory region? for further informa- tion. note that the acc function and unlock bypass modes are not available when the secsi sector is en- abled. word program command sequence programming is a four-bus-cycle operation. the pro- gram command sequence is initiated by writing two unlock write cycles, followed by the program set-up command. the program address and data are written identifier code a7:a0 (x16) a6:a-1 (x8) manufacturer id 00h 00h device id, cycle 1 01h 02h device id, cycle 2 0eh 1ch device id, cycle 3 0fh 1eh secsi sector factory protect 03h 06h sector protect verify (sa)02h (sa)04h
june 10, 2003 am41lv3204m 27 preliminary next, which in turn initiate the embedded program al- gorithm. the system is not required to provide further controls or timings. the device automatically provides internally generated program pulses and verifies the programmed cell margin. tables 10 and 13 show the address and data requirements for the word program command sequence. when the embedded program algorithm is complete, the device then returns to the read mode and ad- dresses are no longer latched. the system can deter- mine the status of the program operation by using dq7 or dq6. refer to the write operation status sec- tion for information on these status bits. any commands written to the device during the em- bedded program algorithm are ignored. note that a hardware reset immediately terminates the program operation. the program command sequence should be reinitiated once the device has returned to the read mode, to ensure data integrity. note that the secsi sector, autoselect, and cfi functions are unavailable when a program operation is in progress. programming is allowed in any sequence and across sector boundaries. a bit cannot be programmed from ?0? back to a ?1.? attempting to do so may cause the device to set dq5 = 1, or cause the dq7 and dq6 status bits to indicate the operation was suc- cessful. however, a succeeding read will show that the data is still ?0.? only erase operations can convert a ?0? to a ?1.? unlock bypass command sequence the unlock bypass feature allows the system to pro- gram words to the device faster than using the stan- dard program command sequence. the unlock bypass command sequence is initiated by first writing two unlock cycles. this is followed by a third write cycle containing the unlock bypass command, 20h. the device then enters the unlock bypass mode. a two-cycle unlock bypass program command sequence is all that is required to program in this mode. the first cycle in this sequence contains the unlock bypass pro- gram command, a0h; the second cycle contains the program address and data. additional data is pro- grammed in the same manner. this mode dispenses with the initial two unlock cycles required in the stan- dard program command sequence, resulting in faster total programming time. tables 10 and 13 show the re- quirements for the command sequence. during the unlock bypass mode, only the unlock by- pass program and unlock bypass reset commands are valid. to exit the unlock bypass mode, the system must issue the two-cycle unlock bypass reset com- mand sequence. the first cycle must contain the data 90h. the second cycle must contain the data 00h. the device then returns to the read mode. write buffer programming write buffer programming allows the system write to a maximum of 16 words in one programming operation. this results in faster effective programming time than the standard programming algorithms. the write buffer programming command sequence is initiated by first writing two unlock cycles. this is followed by a third write cycle containing the write buffer load com- mand written at the sector address in which program- ming will occur. the fourth cycle writes the sector address and the number of word locations, minus one, to be programmed. for example, if the system will pro- gram 6 unique address locations, then 05h should be written to the device. this tells the device how many write buffer addresses will be loaded with data and therefore when to expect the program buffer to flash command. the number of locations to program cannot exceed the size of the write buffer or the operation will abort. the fifth cycle writes the first address location and data to be programmed. the write-buffer-page is se- lected by address bits a max ?a 4 . all subsequent ad- dress/data pairs must fall within the selected-write-buffer-page. the system then writes the remaining address/data pairs into the write buffer. write buffer locations may be loaded in any order. the write-buffer-page address must be the same for all address/data pairs loaded into the write buffer. this means write buffer programming cannot be per- formed across multiple write-buffer pages. this also means that write buffer programming cannot be per- formed across multiple sectors. if the system attempts to load programming data outside of the selected write-buffer page, the operation will abort. note that if a write buffer address location is loaded multiple times, the address/data pair counter will be decremented for every data load operation. the host system must therefore account for loading a write-buffer location more than once. the counter decrements for each data load operation, not for each unique write-buffer-address location. note also that if an address location is loaded more than once into the buffer, the final data loaded for that address will be programmed. once the specified number of write buffer locations have been loaded, the system must then write the pro- gram buffer to flash command at the sector address. any other address and data combination aborts the write buffer programming operation. the device then begins programming. data polling should be used while monitoring the last address location loaded into the write buffer. dq7, dq6, dq5, and dq1 should be monitored to determine the device status during write buffer programming.
28 am41lv3204m june 10, 2003 preliminary the write-buffer programming operation can be sus- pended using the standard program suspend/resume commands. upon successful completion of the write buffer programming operation, the device is ready to execute the next command. the write buffer programming sequence can be aborted in the following ways: load a value that is greater than the page buffer size during the number of locations to program step. write to an address in a sector different than the one specified during the write-buffer-load com- mand. write an address/data pair to a different write-buffer-page than the one selected by the starting address during the write buffer data load- ing stage of the operation. write data other than the confirm command after the specified number of data load cycles. the abort condition is indicated by dq1 = 1, dq7 = data# (for the last address location loaded), dq6 = toggle, and dq5=0. a write-to-buffer-abort reset command sequence must be written to reset the de- vice for the next operation. note that the full 3-cycle write-to-buffer-abort reset command sequence is re- quired when using write-buffer-programming features in unlock bypass mode. accelerated program the device offers accelerated program operations through the wp#/acc pin. when the system asserts v hh on the wp#/acc pin, the device automatically en- ters the unlock bypass mode. the system may then write the two-cycle unlock bypass program command sequence. the device uses the higher voltage on the wp#/acc pin to accelerate the operation. note that the wp#/ acc pin must not be at v hh for operations other than accelerated programming, or device dam- age may result. in addition, no external pullup is nec- essary since the wp#/acc pin has internal pullup to v cc . figure 5 illustrates the algorithm for the program oper- ation. refer to the flash erase and program opera- tions table in the ac characteristics section for parameters, and figure 17 for timing diagrams.
june 10, 2003 am41lv3204m 29 preliminary figure 4. write buffer programming operation write ?write to buffer? command and sector address write number of addresses to program minus 1(wc) and sector address write program buffer to flash sector address write first address/data write to a different sector address fail or abort pass read dq7 - dq0 at last loaded address read dq7 - dq0 with address = last loaded address write next address/data pair wc = wc - 1 wc = 0 ? part of ?write to buffer? command sequence ye s ye s ye s ye s ye s ye s no no no no no no abort write to buffer operation? dq7 = data? dq7 = data? dq5 = 1? dq1 = 1? write to buffer aborted. must write ?write-to-buffer abort reset? command sequence to return to read mode. notes: 1. when sector address is specified, any address in the selected sector is acceptable. however, when loading write-buffer address locations with data, all addresses must fall within the selected write-buffer page. 2. dq7 may change simultaneously with dq5. therefore, dq7 should be verified. 3. if this flowchart location was reached because dq5= ?1?, then the device failed. if this flowchart location was reached because dq1= ?1?, then the write to buffer operation was aborted. in either case, the proper reset command must be written before the device can begin another operation. if dq1=1, write the write-buffer-programming-abort-reset command. if dq5=1, write the reset command. 4. see tables 10 and 13 for command sequences required for write buffer programming. (note 3) (note 1) (note 2)
30 am41lv3204m june 10, 2003 preliminary figure 5. program operation program suspend/program resume command sequence the program suspend command allows the system to interrupt a programming operation or a write to buffer programming operation so that data can be read from any non-suspended sector. when the program sus- pend command is written during a programming pro- cess, the device halts the program operation within 15 s maximum (5 s typical) and updates the status bits. addresses are not required when writing the program suspend command. after the programming operation has been sus- pended, the system can read array data from any non-suspended sector. the program suspend com- mand may also be issued during a programming oper- ation while an erase is suspended. in this case, data may be read from any addresses not in erase sus- pend or program suspend. if a read is needed from the secsi sector area (one-time program area), then user must use the proper command sequences to enter and exit this region. the system may also write the autoselect command sequence when the device is in the program suspend mode. the system can read as many autoselect codes as required. when the device exits the autose- lect mode, the device reverts to the program suspend mode, and is ready for another valid operation. see autoselect command sequence for more information. after the program resume command is written, the device reverts to programming. the system can de- termine the status of the program operation using the dq7 or dq6 status bits, just as in the standard pro- gram operation. see write operation status for more information. the system must write the program resume com- mand (address bits are don?t care) to exit the program suspend mode and continue the programming opera- tion. further writes of the resume command are ig- nored. another program suspend command can be written after the device has resume programming. start write program command sequence data poll from system verify data? no yes last address? no yes programming completed increment address embedded program algorithm in progress note: see tables 10 and 13 for program command sequence.
june 10, 2003 am41lv3204m 31 preliminary figure 6. program suspend/program resume chip erase command sequence chip erase is a six bus cycle operation. the chip erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. two additional unlock write cycles are then followed by the chip erase command, which in turn invokes the embedded erase algorithm. the device does not require the system to preprogram prior to erase. the embedded erase algo- rithm automatically preprograms and verifies the entire memory for an all zero data pattern prior to electrical erase. the system is not required to provide any con- trols or timings during these operations. tables 10 and 13 shows the address and data requirements for the chip erase command sequence. note that the secsi sector, autoselect, and cfi functions are unavailable when a program operation is in progress. when the embedded erase algorithm is complete, the device returns to the read mode and addresses are no longer latched. the system can determine the status of the erase operation by using dq7, dq6, or dq2. refer to the write operation status section for infor- mation on these status bits. any commands written during the chip erase operation are ignored. however, note that a hardware reset im- mediately terminates the erase operation. if that oc- curs, the chip erase command sequence should be reinitiated once the device has returned to reading array data, to ensure data integrity. figure 7 illustrates the algorithm for the erase opera- tion. refer to the flash erase and program opera- tions tables in the ac characteristics section for parameters, and figure 19 section for timing dia- grams. sector erase command sequence sector erase is a six bus cycle operation. the sector erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. two ad- ditional unlock cycles are written, and are then fol- lowed by the address of the sector to be erased, and the sector erase command. tables 10 and 13 shows the address and data requirements for the sector erase command sequence. note that the secsi sec- tor, autoselect, and cfi functions are unavailable when a program operation is in progress. the device does not require the system to preprogram prior to erase. the embedded erase algorithm auto- matically programs and verifies the entire memory for an all zero data pattern prior to electrical erase. the system is not required to provide any controls or tim- ings during these operations. after the command sequence is written, a sector erase time-out of 50 s occurs. during the time-out period, additional sector addresses and sector erase com- mands may be written. loading the sector erase buffer may be done in any sequence, and the number of sec- tors may be from one sector to all sectors. the time between these additional cycles must be less than 50 s, otherwise erasure may begin. any sector erase address and command following the exceeded time-out may or may not be accepted. it is recom- mended that processor interrupts be disabled during this time to ensure all commands are accepted. the interrupts can be re-enabled after the last sector erase command is written. any command other than sector erase or erase suspend during the time-out period resets the device to the read mode. the system must rewrite the command se- quence and any additional addresses and commands. the system can monitor dq3 to determine if the sec- tor erase timer has timed out (see the section on dq3: program operation or write-to-buffer sequence in progress write program suspend command sequence command is also valid for erase-suspended-program operations autoselect and secsi sector read operations are also allowed data cannot be read from erase- o r program-suspended sectors write program resume command sequence read data as required done reading? no yes write address/data xxxh/30h device reverts to operation prior to program suspend write address/data xxxh/b0h wait 15 s
32 am41lv3204m june 10, 2003 preliminary sector erase timer.). the time-out begins from the ris- ing edge of the final we# pulse in the command sequence. when the embedded erase algorithm is complete, the device returns to reading array data and addresses are no longer latched. the system can determine the status of the erase operation by reading dq7, dq6, or dq2 in the erasing sector. refer to the write opera- tion status section for information on these status bits. once the sector erase operation has begun, only the erase suspend command is valid. all other com- mands are ignored. however, note that a hardware reset immediately terminates the erase operation. if that occurs, the sector erase command sequence should be reinitiated once the device has returned to reading array data, to ensure data integrity. figure 7 illustrates the algorithm for the erase opera- tion. refer to the flash erase and program opera- tions tables in the ac characteristics section for parameters, and figure 19 section for timing dia- grams. figure 7. erase operation erase suspend/erase resume commands the erase suspend command, b0h, allows the sys- tem to interrupt a sector erase operation and then read data from, or program data to, any sector not selected for erasure. this command is valid only during the sector erase operation, including the 50 s time-out period during the sector erase command sequence. the erase suspend command is ignored if written dur- ing the chip erase operation or embedded program algorithm. when the erase suspend command is written during the sector erase operation, the device requires a typi- cal of 5 s (maximum of 20 s) to suspend the erase operation. however, when the erase suspend com- mand is written during the sector erase time-out, the device immediately terminates the time-out period and suspends the erase operation. after the erase operation has been suspended, the device enters the erase-suspend-read mode. the sys- tem can read data from or program data to any sector not selected for erasure. (the device ?erase sus- pends? all sectors selected for erasure.) reading at any address within erase-suspended sectors pro- duces status information on dq7?dq0. the system can use dq7, or dq6 and dq2 together, to determine if a sector is actively erasing or is erase-suspended. refer to the write operation status section for infor- mation on these status bits. after an erase-suspended program operation is com- plete, the device returns to the erase-suspend-read mode. the system can determine the status of the program operation using the dq7 or dq6 status bits, just as in the standard word program operation. refer to the write operation status section for more information. in the erase-suspend-read mode, the system can also issue the autoselect command sequence. refer to the autoselect mode and autoselect command sequence sections for details. to resume the sector erase operation, the system must write the erase resume command. the address of the erase-suspended sector is required when writ- ing this command. further writes of the resume com- mand are ignored. another erase suspend command can be written after the chip has resumed erasing. start write erase command sequence (notes 1, 2) data poll to erasing bank from system data = ffh? no yes erasure completed embedded erase algorithm in progress notes: 1. see tables 10 and 13 for erase command sequence. 2. see the section on dq3 for information on the sector erase timer.
june 10, 2003 am41lv3204m 33 preliminary command definitions table 13. command definitions (flash, x16 mode, ciof = v ih ) legend: x = don?t care ra = read address of the memory location to be read. rd = read data read from location ra during read operation. pa = program address . addresses latch on the falling edge of the we# or ce# pulse, whichever happens later. pd = program data for location pa. data latches on the rising edge of we# or ce# pulse, whichever happens first. sa = sector address of sector to be verified (in autoselect mode) or erased. address bits a20?a15 uniquely select any sector. wbl = write buffer location. address must be within the same write buffer page as pa. wc = word count. number of write buffer locations to load minus 1. notes: 1. see table 1 for description of bus operations. 2. all values are in hexadecimal. 3. except for the read cycle and the fourth cycle of the autoselect command sequence, all bus cycles are write cycles. 4. during unlock cycles, when lower address bits are 555 or 2aah as shown in table, address bits higher than a11 (except where ba, pa, or sa is required) and data bits higher than dq7 are don?t cares. 5. no unlock or command cycles required when device is in read mode. 6. the reset command is required to return to the read mode (or to the erase-suspend-read mode if previously in erase suspend) when the device is in the autoselect mode, or if dq5 goes high while the device is providing status information. 7. the fourth cycle of the autoselect command sequence is a read cycle. data bits dq15?dq8 are don?t care except for rd, pd, and wc. see the autoselect command sequence section for more information. 8. the device id must be read in three cycles. the data is 2201h for top boot. 9. wp# protects the top two address sectors, the data is 98h for factory locked and 18h for not factory locked. 10. the data is 00h for an unprotected sector group and 01h for a protected sector group. 11. the total number of cycles in the command sequence is determined by the number of words written to the write buffer. the maximum number of cycles in the command sequence is 21. 12. command sequence resets device for next command after aborted write-to-buffer operation. 13. the unlock bypass command is required prior to the unlock bypass program command. 14. the unlock bypass reset command is required to return to the read mode when the device is in the unlock bypass mode. 15. the system may read and program in non-erasing sectors, or enter the autoselect mode, when in the erase suspend mode. the erase suspend command is valid only during a sector erase operation. 16. the erase resume command is valid only during the erase suspend mode. 17. command is valid when device is ready to read array data or when device is in autoselect mode. command sequence (notes) cycles bus cycles (notes 1?4) first second third fourth fifth sixth addr data addr data addr data addr data addr data addr data read (note 5) 1 ra rd reset (note 6) 1 xxx f0 autoselect (note 7) manufacturer id 4 555 aa 2aa 55 555 90 x00 0001 device id (note 8) 6 555 aa 2aa 55 555 90 x01 227e x0e 221a x0f 2201 secsi ? sector factory protect (note 9) 4 555 aa 2aa 55 555 90 x03 (note 9) sector group protect verify (note 10) 4 555 aa 2aa 55 555 90 (sa)x02 00/01 enter secsi sector region 3 555 aa 2aa 55 555 88 exit secsi sector region 4 555 aa 2aa 55 555 90 xxx 00 program 4 555 aa 2aa 55 555 a0 pa pd write to buffer (note 11) 6 555 aa 2aa 55 sa 25 sa wc pa pd wbl pd program buffer to flash 1 sa 29 write to buffer abort reset (note 12) 3 555 aa 2aa 55 555 f0 unlock bypass 3 555 aa 2aa 55 555 20 unlock bypass program (note 13) 2 xxx a0 pa pd unlock bypass reset (note 14) 2 xxx 90 xxx 00 chip erase 6 555 aa 2aa 55 555 80 555 aa 2aa 55 555 10 sector erase 6 555 aa 2aa 55 555 80 555 aa 2aa 55 sa 30 program/erase suspend (note 15) 1 ba b0 program/erase resume (note 16) 1 ba 30 cfi query (note 17) 1 55 98
34 am41lv3204m june 10, 2003 preliminary table 14. command definitions (flash x8 mode, ciof = v il ) legend: x = don?t care ra = read address of the memory location to be read. rd = read data read from location ra during read operation. pa = program address . addresses latch on the falling edge of the we# or ce# pulse, whichever happens later. pd = program data for location pa. data latches on the rising edge of we# or ce# pulse, whichever happens first. sa = sector address of sector to be verified (in autoselect mode) or erased. address bits a20?a15 uniquely select any sector. wbl = write buffer location. address must be within the same write buffer page as pa. bc = byte count. number of write buffer locations to load minus 1. notes: 1. see table 1 for description of bus operations. 2. all values are in hexadecimal. 3. except for the read cycle and the fourth cycle of the autoselect command sequence, all bus cycles are write cycles. 4. during unlock cycles, when lower address bits are 555 or aaah as shown in table, address bits higher than a11 (except where ba is required) and data bits higher than dq7 are don?t cares. 5. no unlock or command cycles required when device is in read mode. 6. the reset command is required to return to the read mode (or to the erase-suspend-read mode if previously in erase suspend) when the device is in the autoselect mode, or if dq5 goes high while the device is providing status information. 7. the fourth cycle of the autoselect command sequence is a read cycle. data bits dq15?dq8 are don?t care. see the autoselect command sequence section for more information. 8. the device id must be read in three cycles. the data is 01h for top boot and 00h for bottom boot 9. if wp# protects the top two address sectors, the data is 98h for factory locked and 18h for not factory locked. if wp# protects the bottom two address sectors, the data is 88h for factory locked and 08h for not factor locked. 10. the data is 00h for an unprotected sector group and 01h for a protected sector group. 11. the total number of cycles in the command sequence is determined by the number of words written to the write buffer. the maximum number of cycles in the command sequence is 37. 12. command sequence resets device for next command after aborted write-to-buffer operation. 13. the unlock bypass command is required prior to the unlock bypass program command. 14. the unlock bypass reset command is required to return to the read mode when the device is in the unlock bypass mode. 15. the system may read and program in non-erasing sectors, or enter the autoselect mode, when in the erase suspend mode. the erase suspend command is valid only during a sector erase operation. 16. the erase resume command is valid only during the erase suspend mode. 17. command is valid when device is ready to read array data or when device is in autoselect mode. command sequence (notes) cycles bus cycles (notes 1?4) first second third fourth fifth sixth addr data addr data addr data addr data addr data addr data read (note 5) 1 ra rd reset (note 6) 1 xxx f0 autoselect (note 7) manufacturer id 4 aaa aa 555 55 aaa 90 x00 01 device id (note 8) 6 aaa aa 555 55 aaa 90 x02 7e x1c 1a x1e 00/01 secsi ? sector factory protect (note 9) 4 aaa aa 555 55 aaa 90 x06 (note 9) sector group protect verify (note 10) 4 aaa aa 555 55 aaa 90 (sa)x04 00/01 enter secsi sector region 3 aaa aa 555 55 aaa 88 exit secsi sector region 4 aaa aa 555 55 aaa 90 xxx 00 program 4 aaa aa 555 55 aaa a0 pa pd write to buffer (note 11) 6 aaa aa 555 55 sa 25 sa bc pa pd wbl pd program buffer to flash 1 sa 29 write to buffer abort reset (note 12) 3 aaa aa 555 55 aaa f0 unlock bypass 3 aaa aa 555 55 aaa 20 unlock bypass program (note 13) 2 xxx a0 pa pd unlock bypass reset (note 14) 2 xxx 90 xxx 00 chip erase 6 aaa aa 555 55 aaa 80 aaa aa 555 55 aaa 10 sector erase 6 aaa aa 555 55 aaa 80 aaa aa 555 55 sa 30 program/erase suspend (note 15) 1 ba b0 program/erase resume (note 16) 1 ba 30 cfi query (note 17) 1 aa 98
june 10, 2003 am41lv3204m 35 preliminary write operation status the device provides several bits to determine the status of a program or erase operation: dq2, dq3, dq5, dq6, and dq7. ta b l e 11 and the following subsections describe the function of these bits. dq7 and dq6 each offer a method for determining whether a program or erase operation is complete or in progress. the device also provides a hardware-based output signal, ry/by#, to determine whether an embedded program or erase operation is in progress or has been completed. dq7: data# polling the data# polling bit, dq7, indicates to the host system whether an embedded program or erase algorithm is in progress or completed, or whether the device is in erase suspend. data# polling is valid after the rising edge of the final we# pulse in the command sequence. during the embedded program algorithm, the device out- puts on dq7 the complement of the datum programmed to dq7. this dq7 status also applies to programming during erase suspend. when the embedded program algorithm is complete, the device outputs the datum programmed to dq7. the system must provide the program address to read valid status information on dq7. if a program address falls within a protected sector, data# polling on dq7 is ac- tive for approximately 1 s, then the device returns to the read mode. during the embedded erase algorithm, data# polling produces a ?0? on dq7. when the embedded erase algorithm is complete, or if the device enters the erase suspend mode, data# polling produces a ?1? on dq7. the system must provide an address within any of the sectors selected for erasure to read valid status infor- mation on dq7. after an erase command sequence is written, if all sectors selected for erasing are protected, data# poll- ing on dq7 is active for approximately 100 s, then the device returns to the read mode. if not all selected sectors are protected, the embedded erase algorithm erases the unprotected sectors, and ignores the se- lected sectors that are protected. however, if the sys- tem reads dq7 at an address within a protected sector, the status may not be valid. just prior to the completion of an embedded program or erase operation, dq7 may change asynchronously with dq0?dq6 while output enable (oe#) is asserted low. that is, the device may change from providing status information to valid data on dq7. depending on when the system samples the dq7 output, it may read the status or valid data. even if the device has com- pleted the program or erase operation and dq7 has valid data, the data outputs on dq0?dq6 may be still invalid. valid data on dq0?dq7 will appear on suc- cessive read cycles. ta b l e 11 shows the outputs for data# polling on dq7. figure 8 shows the data# polling algorithm. figure 20 in the ac characteristics section shows the data# polling timing diagram. figure 8. data# polling algorithm dq7 = data? yes no no dq5 = 1? no yes yes fail pass read dq7?dq0 addr = va read dq7?dq0 addr = va dq7 = data? start notes: 1. va = valid address for programming. during a sector erase operation, a valid address is any sector address within the sector being erased. during chip erase, a valid address is any non-protected sector address. 2. dq7 should be rechecked even if dq5 = ?1? because dq7 may change simultaneously with dq5.
36 am41lv3204m june 10, 2003 preliminary ry/by#: ready/busy# the ry/by# is a dedicated, open-drain output pin which indicates whether an embedded algorithm is in progress or complete. the ry/by# status is valid after the rising edge of the final we# pulse in the command sequence. since ry/by# is an open-drain output, sev- eral ry/by# pins can be tied together in parallel with a pull-up resistor to v cc . if the output is low (busy), the device is actively eras- ing or programming. (this includes programming in the erase suspend mode.) if the output is high (ready), the device is in the read mode, the standby mode, or in the erase-suspend-read mode. table 11 shows the outputs for ry/by#. dq6: toggle bit i toggle bit i on dq6 indicates whether an embedded program or erase algorithm is in progress or com- plete, or whether the device has entered the erase suspend mode. toggle bit i may be read at any ad- dress, and is valid after the rising edge of the final we# pulse in the command sequence (prior to the program or erase operation), and during the sector erase time-out. during an embedded program or erase algorithm op- eration, successive read cycles to any address cause dq6 to toggle. the system may use either oe# or ce# to control the read cycles. when the operation is complete, dq6 stops toggling. after an erase command sequence is written, if all sectors selected for erasing are protected, dq6 toggles for approxi- mately 100 s, then returns to reading array data. if not all selected sectors are protected, the embedded erase algo- rithm erases the unprotected sectors, and ignores the se- lected sectors that are protected. the system can use dq6 and dq2 together to determine whether a sector is actively erasing or is erase-suspended. when the device is actively erasing (that is, the embedded erase algorithm is in progress), dq6 toggles. when the de- vice enters the erase suspend mode, dq6 stops toggling. however, the system must also use dq2 to determine which sectors are erasing or erase-suspended. alterna- tively, the system can use dq7 (see the subsection on dq7: data# polling ). if a program address falls within a protected sector, dq6 toggles for approximately 1 s after the program command sequence is written, then returns to reading array data. dq6 also toggles during the erase-suspend-program mode, and stops toggling once the embedded pro- gram algorithm is complete. ta b l e 11 shows the outputs for toggle bit i on dq6. figure 9 shows the toggle bit algorithm. figure 21 in the ?ac characteristics? section shows the toggle bit timing diagrams. figure 22 shows the differences be- tween dq2 and dq6 in graphical form. see also the subsection on dq2: toggle bit ii .
june 10, 2003 am41lv3204m 37 preliminary figure 9. toggle bit algorithm dq2: toggle bit ii the ?toggle bit ii? on dq2, when used with dq6, indi- cates whether a particular sector is actively erasing (that is, the embedded erase algorithm is in progress), or whether that sector is erase-suspended. toggle bit ii is valid after the rising edge of the final we# pulse in the command sequence. dq2 toggles when the system reads at addresses within those sectors that have been selected for era- sure. (the system may use either oe# or ce# to con- trol the read cycles.) but dq2 cannot distinguish whether the sector is actively erasing or is erase-sus- pended. dq6, by comparison, indicates whether the device is actively erasing, or is in erase suspend, but cannot distinguish which sectors are selected for era- sure. thus, both status bits are required for sector and mode information. refer to table 11 to compare out- puts for dq2 and dq6. figure 9 shows the toggle bit algorithm in flowchart form, and the section ?dq2: toggle bit ii? explains the algorithm. see also the ry/by#: ready/busy# sub- section. figure 21 shows t he toggle bit timing diagram. figure 22 shows the differences between dq2 and dq6 in graphical form. reading toggle bits dq6/dq2 refer to figure 9 for the following discussion. when- ever the system initially begins reading toggle bit sta- tus, it must read dq7?dq0 at least twice in a row to determine whether a toggle bit is toggling. typically, the system would note and store the value of the tog- gle bit after the first read. after the second read, the system would compare the new value of the toggle bit with the first. if the toggle bit is not toggling, the device has completed the program or erase operation. the system can read array data on dq7?dq0 on the fol- lowing read cycle. however, if after the initial two read cycles, the system determines that the toggle bit is still toggling, the sys- tem also should note whether the value of dq5 is high (see the section on dq5). if it is, the system should then determine again whether the toggle bit is tog- gling, since the toggle bit may have stopped toggling just as dq5 went high. if the toggle bit is no longer toggling, the device has successfully completed the program or erase operation. if it is still toggling, the de- vice did not completed the operation successfully, and the system must write the reset command to return to reading array data. the remaining scenario is that the system initially de- termines that the toggle bit is toggling and dq5 has not gone high. the system may continue to monitor the toggle bit and dq5 through successive read cy- cles, determining the status as described in the previ- ous paragraph. alternatively, it may choose to perform start no yes yes dq5 = 1? no yes toggle bit = toggle? no program/erase operation not complete, write reset command program/erase operation complete read dq7?dq0 toggle bit = toggle? read dq7?dq0 twice read dq7?dq0 note: the system should recheck the toggle bit even if dq5 = ?1? because the toggle bit may stop toggling as dq5 changes to ?1.? see the subsections on dq6 and dq2 for more information.
38 am41lv3204m june 10, 2003 preliminary other system tasks. in this case, the system must start at the beginning of the algorithm when it returns to de- termine the status of the operation (top of figure 9). dq5: exceeded timing limits dq5 indicates whether the program, erase, or write-to-buffer time has exceeded a specified internal pulse count limit. under these conditions dq5 produces a ?1,? indicating that the program or erase cycle was not suc- cessfully completed. the device may output a ?1? on dq5 if the system tries to program a ?1? to a location that was previously pro- grammed to ?0.? only an erase operation can change a ?0? back to a ?1.? under this condition, the device halts the operation, and when the timing limit has been exceeded, dq5 produces a ?1.? in all these cases, the system must write the reset command to return the device to the reading the array (or to erase-suspend-read if the device was previously in the erase-suspend-program mode). dq3: sector erase timer after writing a sector erase command sequence, the system may read dq3 to determine whether or not erasure has begun. (the sector erase timer does not apply to the chip erase command.) if additional sectors are selected for erasure, the entire time-out also applies after each additional sector erase com- mand. when the time-out period is complete, dq3 switches from a ?0? to a ?1.? if the time between addi- tional sector erase commands from the system can be assumed to be less than 50 s, the system need not monitor dq3. see also the sector erase command sequence section. after the sector erase command is written, the system should read the status of dq7 (data# polling) or dq6 (toggle bit i) to ensure that the device has accepted the command sequence, and then read dq3. if dq3 is ?1,? the embedded erase algorithm has begun; all fur- ther commands (except erase suspend) are ignored until the erase operation is complete. if dq3 is ?0,? the device will accept additional sector erase commands. to ensure the command has been accepted, the sys- tem software should check the status of dq3 prior to and following each subsequent sector erase com- mand. if dq3 is high on the second status check, the last command might not have been accepted. table 11 shows the status of dq3 relative to the other status bits. dq1: write-to-buffer abort dq1 indicates whether a write-to-buffer operation was aborted. under these conditions dq1 produces a ?1?. the system must issue the write-to-buffer-abort-reset command sequence to re- turn the device to reading array data. see write buffer table 15. write operation status notes: 1. dq5 switches to ?1? when an embedded program, embedded erase, or write-to-buffer operation has exceeded the maximum timing limits. refer to the section on dq5 for more information. 2. dq7 and dq2 require a valid address when reading status information. refer to the appropriate subsection for further details. 3. the data# polling algorithm should be used to monitor the last loaded write-buffer address location. 4. dq1 switches to ?1? when tthe device has aborted the write-to-buffer operation. status dq7 (note 2) dq6 dq5 (note 1) dq3 dq2 (note 2) dq1 ry/by# standard mode embedded program algorithm dq7# toggle 0 n/a no toggle 0 0 embedded erase algorithm 0 toggle 0 1 toggle n/a 0 program suspend mode program- suspend read program-suspended sector invalid (not allowed) 1 non-program suspended sector data 1 erase suspend mode erase- suspend read erase-suspended sector 1 no toggle 0 n/a toggle n/a 1 non-erase suspended sector data 1 erase-suspend-program (embedded program) dq7# toggle 0 n/a n/a n/a 0 write-to- buffer busy (note 3) dq7# toggle 0 n/a n/a 0 0 abort (note 4) dq7# toggle 0 n/a n/a 1 0
june 10, 2003 am41lv3204m 39 preliminary absolute maximum ratings storage temperature plastic packages . . . . . . . . . . . . . . . ?65 c to +150 c ambient temperature with power applied . . . . . . . . . . . . . ?65 c to +125 c voltage with respect to ground v cc f/v cc s (note 1) . . . . . . . . . . . .?0.3 v to +4.0 v reset#f (note 2). . . . . . . . . . . . ?0.5 v to +12.5 v wp#/acc . . . . . . . . . . . . . . . . . . ?0.5 v to +10.5 v all other pins (note 1) . . . . . . ?0.5 v to v cc +0.5 v output short circuit current (note 3) . . . . . . 200 ma notes: 1. minimum dc voltage on input or i/o pins is ?0.5 v. during voltage transitions, input or i/o pins may overshoot v ss to ?2.0 v for periods of up to 20 ns. maximum dc voltage on input or i/o pins is v cc +0.5 v. see figure 10. during voltage transitions, input or i/o pins may overshoot to v cc +2.0 v for periods up to 20 ns. see figure 11. 2. minimum dc input voltage on pins a9, oe#, acc, and reset# is ?0.5 v. during voltage transitions, a9, oe#, acc, and reset# may overshoot v ss to ?2.0 v for periods of up to 20 ns. see figure 10. maximum dc input voltage on pin a9, oe#, acc, and reset# is +12.5 v which may overshoot to +14.0 v for periods up to 20 ns. 3. no more than one output may be shorted to ground at a time. duration of the short circuit should not be greater than one second. stresses above those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this data sheet is not implied. exposure of the device to absolute maximum rating conditions for extended periods may affect device reliability. operating ranges industrial (i) devices ambient temperature (t a ) . . . . . . . . . ?40c to +85c supply voltages v cc f/v cc s for full voltage range . . . . . . . . . . 2.7?3.3 v note: operating ranges define those limits between which the functionality of the device is guaranteed. 20 ns 20 ns +0.8 v ?0.5 v 20 ns ?2.0 v figure 10. maximum negative overshoot waveform 20 ns 20 ns v cc +2.0 v v cc +0.5 v 20 ns 2.0 v figure 11. maximum positive overshoot waveform
40 am41lv3204m june 10, 2003 preliminary dc characteristics cmos compatible notes: 1. on the wp#/acc pin only, the maximum input load current when wp# = v il is 5.0 a. 2. the i cc current listed is typically less than 2 ma/mhz, with oe# at v ih . 3. maximum i cc specifications are tested with v cc = v cc max. 4. i cc active while embedded erase or embedded program is in progress. 5. automatic sleep mode enables the low power mode when addresses remain stable for t acc + 30 ns. typical sleep mode current is 200 na. 6. v cc voltage requirements. 7. not 100% tested. parameter symbol parameter description (notes) test conditions min typ max unit i li input load current (1) v in = v ss to v cc , v cc = v cc max 1.0 a i lit a9, acc input load current v cc = v cc max ; a9 = 12.5 v 35 a i lr reset leakage current v cc = v cc max ; reset# = 12.5 v 35 a i lo output leakage current v out = v ss to v cc , v cc = v cc max 1.0 a i cc1 v cc active read current (2, 3) ce# = v il, oe# = v ih , 5 mhz 15 20 ma 1 mhz 15 20 i cc2 v cc initial page read current (2, 3) ce# = v il, oe# = v ih 30 50 ma i cc3 v cc intra-page read current (2, 3) ce# = v il, oe# = v ih 10 20 ma i cc4 v cc active write current (3, 4) ce# = v il, oe# = v ih 50 60 ma i cc5 v cc standby current (3) ce#, reset# = v cc 0.3 v, wp# = v ih 15a i cc6 v cc reset current (3) reset# = v ss 0.3 v, wp# = v ih 15a i cc7 automatic sleep mode (3, 5) v ih = v cc 0.3 v; v il = v ss 0.3 v, wp# = v ih 15a v il input low voltage (6) ?0.5 0.8 v v ih input high voltage (6) 0.7 x v cc v cc + 0.5 v v id voltage for autoselect and temporary sector unprotect v cc = 2.7 ?3.6 v 11.5 12.5 v v ol output low voltage i ol = 4.0 ma, v cc = v cc min = v io 0.15 x v cc v v oh1 output high voltage i oh = ?2.0 ma, v cc = v cc min = v io 0.85 v cc v v oh2 i oh = ?100 a, v cc = v cc min = v io v cc ?0.4 v v lko low v cc lock-out voltage (7) 2.3 2.5 v
june 10, 2003 am41lv3204m 41 preliminary sram dc and operating characteristics parameter symbol parameter description test conditions min typ max unit i li input leakage current v in = v ss to v cc ?1.0 1.0 a i lo output leakage current ce1#s = v ih , ce2s = v il or oe# = v ih or we# = v il , v io = v ss to v cc ?1.0 1.0 a i cc operating power supply current i io = 0 ma, ce1#s = v il , ce2s = we# = v ih , v in = v ih or v il 3ma i cc1 s average operating current cycle time = 1 s, 100% duty, i io = 0 ma, ce1#s 0.2 v, ce2 v cc ? 0.2 v, v in 0.2 v or v in v cc ? 0.2 v, cios = v ss or v cc 3ma i cc2 s average operating current cycle time = min., i io = 0 ma, 100% duty, ce1#s = v il , ce2s = v ih , v in = v il = or v ih , cios = v ss or v cc 30 ma v ol output low voltage i ol = 2.1 ma 0.4 v v oh output high voltage i oh = ?1.0 ma 2.4 v i sb standby current (ttl) ce1#s = v ih , ce2 = v il , other inputs = v ih or v il 0.3 ma i sb1 standby current (cmos) ce1#s v cc ? 0.2 v, ce2 v cc ? 0.2 v (ce1#s controlled) or ce2 0.2 v (ce2s controlled) other input = 0 ~ v cc , cios = v ss or v cc 10 a
42 am41lv3204m june 10, 2003 preliminary test conditions table 16. test specifications key to switching waveforms 2.7 k ? c l 6.2 k ? 3.3 v device under te s t note: diodes are in3064 or equivalent figure 12. test setup test condition all speeds unit output load 1 ttl gate output load capacitance, c l (including jig capacitance) 30 pf input rise and fall times 5 ns input pulse levels 0.0?3.0 v input timing measurement reference levels 1.5 v output timing measurement reference levels 1.5 v waveform inputs outputs steady changing from h to l changing from l to h don?t care, any change permitted changing, state unknown does not apply center line is high impedance state (high z) 3.0 v 0.0 v 1.5 v 1.5 v output measurement level input figure 13. input waveforms and measurement levels
june 10, 2003 am41lv3204m 43 preliminary ac characteristics flash read-only operations notes: 1. not 100% tested. 2. see figure 12 and table 12 for test specifications. parameter description test setup speed jedec std. unit t avav t rc read cycle time (note 1) min 100 ns t avqv t acc address to output delay ce#, oe# = v il max 100 ns t elqv t ce chip enable to output delay oe# = v il max 100 ns t pacc page access time max 30 ns t glqv t oe output enable to output delay max 30 ns t ehqz t df chip enable to output high z (note 1) max 30 ns t ghqz t df output enable to output high z (note 1) max 30 ns t axqx t oh output hold time from addresses, ce# or oe#, whichever occurs first min 0 ns t oeh output enable hold time (note 1) read min 0 ns toggle and data# polling min 10 ns t oh t ce outputs we# addresses ce#f oe# high z output valid high z addresses stable t rc t acc t oeh t rh t oe t rh reset#f t df figure 14. read operation timings
44 am41lv3204m june 10, 2003 preliminary ac characteristics figure 15. page read timings a20 - a2 ce#f oe# a1 - a0 data bus same page aa ab ac ad qa qb qc qd t acc t pac c t pac c t pac c
june 10, 2003 am41lv3204m 45 preliminary ac characteristics hardware reset (reset#) note: not 100% tested. parameter description speed unit jedec std. t ready reset# pin low (not during embedded algorithms) to read mode (see note) max 500 ns t rp reset# pulse width min 500 ns t rh reset high time before read (see note) min 50 ns t rpd reset# low to standby mode min 20 s reset# t rp t ready reset timings not during embedded algorithms ce#f, oe# t rh ce#f, oe# reset timings during embedded algorithms reset# t rp figure 16. reset timings
46 am41lv3204m june 10, 2003 preliminary ac characteristics flash erase and program operations notes: 1. not 100% tested. 2. see the ?ac characteristics? section for more information. 3. for 1?16 words programmed. 4. effective write buffer specification is based upon a 16-word write buffer operation. parameter speed jedec std. description unit t avav t wc write cycle time (note 1) min 100 ns t avwl t as address setup time min 0 ns t aso address setup time to oe# low during toggle bit polling min 15 ns t wlax t ah address hold time min 45 ns t aht address hold time from ce# or oe# high during toggle bit polling min 0 ns t dvwh t ds data setup time min 45 ns t whdx t dh data hold time min 0 ns t oeph output enable high during toggle bit polling min 20 ns t ghwl t ghwl read recovery time before write (oe# high to we# low) min 0 ns t elwl t cs ce# setup time min 0 ns t wheh t ch ce# hold time min 0 ns t wlwh t wp write pulse width min 35 ns t whdl t wph write pulse width high min 30 ns t whwh1 t whwh1 write buffer program operation (notes 2, 3) typ 240 s effective write buffer program operation (notes 2, 4) per word typ 15 s accelerated effective write buffer program operation (notes 2, 4) per word typ 11.8 s single word program operation (note 2) typ 60 s single word accelerated programming operation (note 2) typ 54 s t whwh2 t whwh2 sector erase operation (note 2) typ 0.5 sec t vhh v hh rise and fall time (note 1) min 250 ns t vcs v cc setup time (note 1) min 50 s
june 10, 2003 am41lv3204m 47 preliminary ac characteristics oe# we# ce#f v cc data addresses t ds t ah t dh t wp pd t whwh1 t wc t as t wph t vcs 555h pa pa read status data (last two cycles) a0h t cs status d out program command sequence (last two cycles) t ch pa notes: 1. pa = program address, pd = program data, d out is the true data at the program address. 2. illustration shows device in word mode. figure 17. program operation timings acc t vhh v hh v il or v ih v il or v ih t vhh figure 18. accelerated program timing diagram
48 am41lv3204m june 10, 2003 preliminary ac characteristics oe# ce#f addresses v cc we# data 2aah sa t ah t wp t wc t as t wph 555h for chip erase 10 for chip erase 30h t ds t vcs t cs t dh 55h t ch in progress complete t whwh2 va va erase command sequence (last two cycles) read status data notes: 1. sa = sector address (for sector erase), va = valid address for reading status data (see ?write operation status?. 2. these waveforms are for the word mode. figure 19. chip/sector erase operation timings
june 10, 2003 am41lv3204m 49 preliminary ac characteristics we# ce#f oe# high z t oe high z dq7 dq6?dq0 complement tr u e addresses va t oeh t ce t ch t oh t df va va status data complement status data tr u e valid data valid data t acc t rc note: va = valid address. illustration shows first status cycle after command sequence, last status read cycle, and array data read cycle. figure 20. data# polling timings (during embedded algorithms)
50 am41lv3204m june 10, 2003 preliminary ac characteristics oe# ce#f we# addresses t oeh t dh t aht t aso t oeph t oe valid data (first read) (second read) (stops toggling) t ceph t aht t as dq6/dq2 valid data valid status valid status valid status note: va = valid address; not required for dq6. illustration shows first two status cycle after command sequence, last status read cycle, and array data read cycle figure 21. toggle bit timings (during embedded algorithms) note: dq2 toggles only when read at an address within an erase-suspended sector. the system may use oe# or ce# to toggle dq2 and dq6. figure 22. dq2 vs. dq6 enter erase erase erase enter erase suspend program erase suspend read erase suspend read erase we# dq6 dq2 erase complete erase suspend suspend program resume embedded erasing
june 10, 2003 am41lv3204m 51 preliminary ac characteristics temporary sector unprotect note: not 100% tested. parameter all speed options jedec std description unit t vidr v id rise and fall time (see note) min 500 ns t rsp reset# setup time for temporary sector unprotect min 4 s reset# t vidr v id v ss , v il , or v ih v id v ss , v il , or v ih ce# we# t vidr t rsp program or erase command sequence figure 23. temporary sector gr oup unprotect timing diagram
52 am41lv3204m june 10, 2003 preliminary ac characteristics sector group protect: 150 s, sector group unprot ect: 15 ms 1 s reset# sa, a6, a1, a0 data ce# we# oe# 60h 60h 40h valid* valid* valid* status sector group protect or unprotect verify v id v ih * for sector group protect, a6?a0 = 0xx0010. for sector group unprotect, a6?a0 = 1xx0010. figure 24. sector group protect and unprotect timing diagram
june 10, 2003 am41lv3204m 53 preliminary ac characteristics alternate ce# controlled erase and program operations notes: 1. not 100% tested. 2. see the ?ac characteristics? section for more information. 3. for 1?16 words programmed. 4. effective write buffer specification is based upon a 16-word write buffer operation. parameter speed jedec std. description unit t avav t wc write cycle time (note 1) min 100 ns t avwl t as address setup time min 0 ns t elax t ah address hold time min 45 ns t dveh t ds data setup time min 45 ns t ehdx t dh data hold time min 0 ns t ghel t ghel read recovery time before write (oe# high to we# low) min 0 ns t wlel t ws we# setup time min 0 ns t ehwh t wh we# hold time min 0 ns t eleh t cp ce# pulse width min 45 ns t ehel t cph ce# pulse width high min 30 ns t whwh1 t whwh1 write buffer program operation (notes 2, 3) typ 240 s effective write buffer program operation (notes 2, 4) per word typ 15 s accelerated effective write buffer program operation (notes 2, 4) per word typ 11.8 s single word program operation (note 2) typ 60 s single word accelerated programming operation (note 2) typ 54 s t whwh2 t whwh2 sector erase operation (note 2) typ 0.5 sec t rh reset# high time before write (note 1) min 50 ns
54 am41lv3204m june 10, 2003 preliminary ac characteristics t ghel t ws oe# ce#f we# reset# t ds data t ah addresses t dh t cp dq7# d out t wc t as t cph pa data# polling a0 for program 55 for erase t rh t whwh1 or 2 t wh pd for program 30 for sector erase 10 for chip erase 555 for program 2aa for erase pa for program sa for sector erase 555 for chip erase t busy notes: 1. figure indicates last two bus cycles of a program or erase operation. 2. pa = program address, sa = sector address, pd = program data. 3. dq7# is the complement of the data written to the device. d out is the data written to the device. figure 25. alternate ce# controlled write (erase/program) operation timings
june 10, 2003 am41lv3204m 55 preliminary ac characteristics sram read cycle figure 26. sram read cycle?address controlled note: ce1#s = oe# = v il , ce2s = we# = v ih , ub#s and/or lb#s = v il parameter symbol description speed option unit 10 t rc read cycle time min 70 ns t aa address access time max 70 ns t co1 , t co2 chip enable to output max 70 ns t oe output enable access time max 35 ns t ba lb#s, ub#s to access time max 70 ns t lz1 , t lz2 chip enable (ce1#s low and ce2s high) to low-z output min 10 ns t blz ub#, lb# enable to low-z output min 10 ns t olz output enable to low-z output min 5 ns t hz1 , t hz2 chip disable to high-z output max 25 ns t bhz ub#s, lb#s disable to high-z output max 25 ns t ohz output disable to high-z output max 25 ns t oh output data hold from address change min 10 ns address data out previous data valid data valid t aa t rc t oh
56 am41lv3204m june 10, 2003 preliminary ac characteristics figure 27. sram read cycle notes: 1. we# = v ih , if cios is low. 2. t hz and t ohz are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels. 3. at any given temperature and voltage condition, t hz (max.) is less than t lz (min.) both for a given device and from device to device interconnection. data valid high-z t rc ce#1s address oe# data out t oh t aa t co1 t oe t olz t blz t lz t ohz ce2s t co2 ub#s, lb#s t bhz t hz t ba
june 10, 2003 am41lv3204m 57 preliminary ac characteristics sram write cycle notes: 1. we# controlled. 2. t cw is measured from ce1#s going low to the end of write. 3. t wr is measured from the end of write to the address change. t wr applied in case a write ends as ce1#s or we# going high. 4. t as is measured from the address valid to the beginning of write. 5. a write occurs during the overlap (t wp ) of low ce#1 and low we#. a write begins when ce1#s goes low and we# goes low when asserting ub#s or lb#s for a single byte operation or simultaneously asserting ub#s and lb#s for a double byte operation. a write ends at the earliest transition when ce1#s goes high and we# goes high. the t wp is measured from the beginning of write to the end of write. figure 28. sram write cycle?we# control parameter symbol description speed option unit 10 t wc write cycle time min 70 ns t cw chip enable to end of write min 60 ns t as address setup time min 0 ns t aw address valid to end of write min 60 ns t bw ub#s, lb#s to end of write min 60 ns t wp write pulse time min 50 ns t wr write recovery time min 0 ns t whz write to output high-z min 0 ns max 20 t dw data to write time overlap min 30 ns t dh data hold from write time min 0 ns t ow end write to output low-z min 5 ns address ce1#s data undefined we# data in data out t wc t cw (see note 1) t aw high-z high-z data valid ce2s t cw (see note 1) t wp (see note 4) t as (see note 3) t wr t dw t dh t ow t whz
58 am41lv3204m june 10, 2003 preliminary ac characteristics notes: 1. ce1#s controlled. 2. t cw is measured from ce1#s going low to the end of write. 3. t wr is measured from the end of write to the address change. t wr applied in case a write ends as ce1#s or we# going high. 4. t as is measured from the address valid to the beginning of write. 5. a write occurs during the overlap (t wp ) of low ce#1 and low we#. a write begins when ce1#s goes low and we# goes low when asserting ub#s or lb#s for a single byte operation or simultaneously asserting ub#s and lb#s for a double byte operation. a write ends at the earliest transition when ce1#s goes high and we# goes high. the t wp is measured from the beginning of write to the end of write. figure 29. sram write cycle?ce1#s control address data valid ub#s, lb#s we# data in data out high-z high-z t wc ce1#s ce2s t aw t as (see note 2 ) t bw t cw (see note 3) t wr (see note 4) t wp (see note 5) t dw t dh
june 10, 2003 am41lv3204m 59 preliminary ac characteristics notes: 1. ub#s and lb#s controlled. 2. t cw is measured from ce1#s going low to the end of write. 3. t wr is measured from the end of write to the address change. t wr applied in case a write ends as ce1#s or we# going high. 4. t as is measured from the address valid to the beginning of write. 5. a write occurs during the overlap (t wp ) of low ce#1 and low we#. a write begins when ce1#s goes low and we# goes low when asserting ub#s or lb#s for a single byte operation or simultaneously asserting ub#s and lb#s for a double byte operation. a write ends at the earliest transition when ce1#s goes high and we# goes high. the t wp is measured from the beginning of write to the end of write. figure 30. sram write cycle?ub#s and lb#s control address data valid ub#s, lb#s we# data in data out high-z high-z t wc ce1#s ce2s t aw t bw t dw t dh t wr (see note 3) t as (see note 4) t cw (see note 2) t cw (see note 2) t wp (see note 5)
60 am41lv3204m june 10, 2003 preliminary erase and programming performance notes: 1. typical program and erase times assume the following conditions: 25 c, 3.0 v v cc , programming specification assume that all bits are programmed to 00h. 2. maximum values are measured at v cc = 3.0, worst case temperature. maximum values are valid up to and including 100,000 program/erase cycles. 3. word/byte programming specification is based upon a single word/byte programming operation not utilizing the write buffer. 4. for 1-16 words or 1-32 bytes programmed in a single write buffer programming operation. 5. effective write buffer specification is calculated on a per-word/per-byte basis for a 16-word/32-byte write buffer operation. 6. in the pre-programming step of the embedded erase algorithm, all bits are programmed to 00h before erasure. 7. system-level overhead is the time required to execute the command sequence (s) for the program command. see table11 for further information on command definitions. 8. the device has a minimum erase and program cycle endurance of 100,000 cycles. flash latchup characteristics note: includes all pins except v cc . test conditions: v cc = 3.0 v, one pin at a time. parameter typ (note 1) max (note 2) unit comments sector erase time 0.5 3.5 sec excludes 00h programming prior to erasure (note 6) chip erase time 32 64 sec single word/byte program time (note 3) byte 60 600 s excludes system level overhead (note 7) word 60 600 s accelerated single word/byte program time (note 3) byte 54 540 s word 54 540 s total write buffer program time (note 4) 240 1200 s effective write buffer program time (note 5) per byte 7.5 38 s per word 15 75 s total accelerated write buffer program time (note 4) 200 1040 s effective accelerated write buffer program time (note 5) per byte 6.25 33 s per word 12.5 65 s chip program time 31.5 73 sec description min max input voltage with respect to v ss on all pins except i/o pins (including oe#, and reset#f) ?1.0 v 12.5 v input voltage with respect to v ss on all i/o pins ?1.0 v v cc + 1.0 v v cc current ?100 ma +100 ma
june 10, 2003 am41lv3204m 61 preliminary package pin capacitance notes: 1. sampled, not 100% tested. 2. test conditions t a = 25c, f = 1.0 mhz. data retention parameter symbol parameter description test setup typ max unit c in input capacitance v in = 0 fine-pitch bga 4.2 5.0 pf c out output capacitance v out = 0 fine-pitch bga 5.4 6.5 pf c in2 control pin capacitance v in = 0 fine-pitch bga 3.9 4.7 pf parameter description test conditions min unit minimum pattern data retention time 150 c10years 125 c20years
62 am41lv3204m june 10, 2003 preliminary sram data retention notes: 1. ce1#s v cc ? 0.2 v, ce2s v cc ? 0.2 v (ce1#s controlled) or ce2s 0.2 v (ce2s controlled). 2. typical values are not 100% tested. figure 31. ce#1 controlled data retention mode figure 32. ce2s controlled data retention mode parameter symbol parameter description test setup min typ max unit v dr v cc for data retention ce1#s v cc ? 0.2 v (note 1) 2.7 3.3 v i dr data retention current v cc = 3.0 v, ce1#s v cc ? 0.2 v (note 1) 1.0 (note 2) 10 a t sdr data retention set-up time see data retention waveforms 0ns t rdr recovery time t rc ns v dr v cc 2.7v 2.2v ce1#s gnd data retention mode ce1#s v cc - 0.2 v t sdr t rdr v cc 2.7 v 0.4 v v dr ce2#s gnd data retention mode t sdr t rdr ce2#s < 0.2 v
physical dimensions ?2003 advanced micro devices, inc . 01/03 printed in usa one amd place, p.o. box 3453, sunnyvale, ca 94088-3453 408-732-2400 twx 910-339-9280 telex 34-6306 800-538-8450 http://www.amd.com advanced micro devices reserves the right to make changes in its product without notice in order to impr ove design or performance characteristics.the performance characteristics listed in this document are guaranteed by specific tests, guard banding, design and other practices common to the industry. for specific testing details, contact your local amd sales representativ e.the company assumes no responsibility for the use of any circuits described herein. ? advanced micro devices, inc. all rights reser ved. amd, the amd arrow logo and combination thereof, are trademarks of advanced micro devices, inc. other product names are for informational purposes only and may be trademarks of their respective companies. north america alabama . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ( 256)830-9192 arizona . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ( 602)242-4400 california, irvine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .(949)450-7500 sunnyvale . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ( 408)732-2400 colorado . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ( 303)741-2900 connecticut . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ( 203)264-7800 florida, clearwater . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ( 7 2 7 ) 7 9 3 - 0055 miami (lakes) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .(305)820-1113 georgia . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ( 770)814-0224 illinois, chicago . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .(630)773-4422 massachusetts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ( 7 8 1 ) 2 1 3 - 6400 michigan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .(248)471-6294 minnesota . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ( 6 1 2 ) 74 5 - 0005 new jersey, chatham . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ( 9 7 3 ) 7 0 1-1777 new york . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ( 7 1 6 ) 4 2 5 - 8050 north carolina . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .(919)840-8080 oregon . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ( 503)245-0080 pennsylvania . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ( 2 1 5 ) 340-1187 south dakota . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ( 605)692-5777 texas, austin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .(512)346-7830 dallas . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .(972)985-1344 houston . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ( 2 8 1 ) 3 76 - 8084 virginia . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .(703)736-9568 international australia, north ryde . . . . . . . . . . . . . . . . . . . . . . . tel(61)2-88-777-222 belgium, antwerpen . . . . . . . . . . . . . . . . . . . . . . . . tel(32)3-248-43-00 brazil, san paulo . . . . . . . . . . . . . . . . . . . . . . . . . . tel(55)11-5501-2105 china, beijing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . tel(86)10-6510-2188 shanghai . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . tel(86)21-635-00838 shenzhen . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . tel(86)755-246-1550 finland, helsinki . . . . . . . . . . . . . . . . . . . . . . tel(358)881-3117 france, paris . . . . . . . . . . . . . . . . . . . . . . . . . . . . tel(33)-1-49751010 germany, bad homburg . . . . . . . . . . . . . . . . . . . . . . . . . . . tel(49)-6172- 92670 munich . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .tel(49)-89-450530 hong kong, causeway bay . . . . . . . . . . . . . . . . . . . tel(85)2-2956-0388 italy,milan . . . . . . . . . . . . . . . . . . . . . . . . . . . . .tel(39)-02-381961 india,new delhi . . . . . . . . . . . . . . . . . . . . . . . . . .tel(91)11-623-8620 japan, osaka . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . tel(81)6-6243-3250 tokyo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .tel(81)3-3346-7600 korea, seoul . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . tel(82)2-3468-2600 russia, moscow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . tel(7)-095-795-06-22 sweden, stockholm . . . . . . . . . . . . . . . . . . . . . . . . . . . tel(46)8-562-540-00 taiwan,taipei . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .tel(886)2-8773-1555 united kingdom, frimley . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .tel(44)1276-803100 haydock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . tel(44)1942-272888 representatives in u.s. and canada arizona, tempe - centaur . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (480)839-2320 california, calabasas - centaur . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ( 8 1 8 ) 878-5800 irvine - centaur . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ( 9 4 9 ) 2 6 1 - 2 1 2 3 san diego - centaur. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (858)278-4950 santa clara - fourfront. . . . . . . . . . . . . . . . . . . . . . . . . . . . ( 408)350-4800 canada, burnaby, b.c. - davetek marketing. . . . . . . . . . . . . . . . . . . . ( 604)430-3680 calgary, alberta - davetek marketing. . . . . . . . . . . . . . . . . ( 403)283-3577 kanata, ontario - j-squared tech. . . . . . . . . . . . . . . . . . . . ( 6 1 3 ) 5 9 2 - 9540 mississauga, ontario - j-squared tech. . . . . . . . . . . . . . . . . . ( 905)672-2030 st laurent, quebec - j-squared tech. . . . . . . . . . . . . . . . ( 5 1 4 ) 7 4 7 - 1 2 1 1 colorado, golden - compass marketing . . . . . . . . . . . . . . . . . . . . . . ( 303)277-0456 florida, melbourne - marathon technical sales . . . . . . . . . . . . . . . . ( 3 2 1 ) 7 2 8 - 7706 ft. lauderdale - marathon technical sales . . . . . . . . . . . . . . ( 954)527-4949 orlando - marathon technical sales . . . . . . . . . . . . . . . . . . ( 407)872-5775 st. petersburg - marathon technical sales . . . . . . . . . . . . . . ( 7 2 7 ) 8 9 4 - 3603 georgia, duluth - quantum marketing . . . . . . . . . . . . . . . . . . . . . ( 6 7 8 ) 584-1128 illinois, skokie - industrial reps, inc. . . . . . . . . . . . . . . . . . . . . . . . . ( 8 4 7 ) 9 6 7 - 8430 indiana, kokomo - sai . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ( 7 6 5 ) 457-7241 iowa, cedar rapids - lorenz sales . . . . . . . . . . . . . . . . . . . . . . ( 3 1 9 ) 2 9 4 - 1 0 0 0 kansas, lenexa - lorenz sales . . . . . . . . . . . . . . . . . . . . . . . . . ( 9 1 3 ) 4 6 9 -1312 massachusetts, burlington - synergy associates . . . . . . . . . . . . . . . . . . . . . ( 7 8 1 ) 238-0870 michigan, brighton - sai . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .(810)227-0007 minnesota, st. paul - cahill, schmitz & cahill, inc. . . . . . . . . . . . . . . . . . ( 6 5 1 ) 69 9 - 0200 missouri, st. louis - lorenz sales . . . . . . . . . . . . . . . . . . . . . . . . . . ( 3 1 4 ) 9 9 7 - 4558 new jersey, mt. laurel - sj associates . . . . . . . . . . . . . . . . . . . . . . . . . ( 856)866-1234 new york, buffalo - nycom, inc. . . . . . . . . . . . . . . . . . . . . . . . . .(716)741-7116 east syracuse - nycom, inc. . . . . . . . . . . . . . . . . . . . . . . ( 3 1 5 ) 437-8343 pittsford - nycom, inc. . . . . . . . . . . . . . . . . . . . . . . . . . . ( 7 1 6 ) 586-3660 rockville centre - sj associates . . . . . . . . . . . . . . . . . . . . ( 5 1 6 ) 536-4242 north carolina, raleigh - quantum marketing . . . . . . . . . . . . . . . . . . . . . . ( 9 1 9 ) 846-5728 ohio, middleburg hts - dolfuss root & co. . . . . . . . . . . . . . . . . ( 440)816-1660 powell - dolfuss root & co. . . . . . . . . . . . . . . . . . . . . . . ( 6 1 4 ) 7 8 1 - 0 7 2 5 vandalia - dolfuss root & co. . . . . . . . . . . . . . . . . . . . . .(937)898-9610 westerville - dolfuss root & co. . . . . . . . . . . . . . . . . . . ( 6 1 4 ) 5 2 3 - 1 9 9 0 oregon, lake oswego - i squared, inc. . . . . . . . . . . . . . . . . . . . . . . ( 503)670-0557 utah, murray - front range marketing . . . . . . . . . . . . . . . . . . . . ( 8 0 1 ) 288-2500 virginia, glen burnie - coherent solution, inc. . . . . . . . . . . . . . . . . ( 4 1 0 ) 7 6 1 - 2255 washington, kirkland - i squar ed,inc. . . . . . . . . . . . . . . . . . . . . . . . . . .(425)822-9220 wisconsin, pewaukee - industrial representatives . . . . . . . . . . . . . . . . ( 2 6 2 ) 5 74 - 9 3 9 3 representatives in latin america argentina, capital f ederal argentina/ww rep. . . . . . . . . . . . . . . . . . . .54 -11)4373-0655 chile, santiago - latinrep/wwrep. . . . . . . . . . . . . . . . . . . . . . . . . .(+562)264-0993 columbia, bogota - dimser. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .(571)410-4182 mexico, guadalajara - latinrep/ww rep. . . . . . . . . . . . . . . . . . . . ( 5 2 3 ) 8 1 7 - 3900 mexico city - latinrep/ww rep. . . . . . . . . . . . . . . . . . . . ( 5 2 5 ) 7 5 2 - 2727 monterrey - latinrep/ww rep. . . . . . . . . . . . . . . . . . . . .(528)369-6828 puert o rico, boqueron - infitronics. . . . . . . . . . . . . . . . . . . . . . . . . . . . (787)851-6000 sales offices and representatives es
64 am41lv3204m june 10, 2003 preliminary tlb069?69-ball fine-pitch ball grid array (fbga) 8 x 10 mm package e1 7 se a d1 ed dc e f g h j k 10 8 9 7 6 4 3 2 1 ee 5 b pin a1 corner 7 sd bottom view c 0.08 0.20 c a e b c 0.15 (2x) c d c 0.15 (2x) index mark 10 6 b top view side view corner 69x a1 a2 a m 0.15 c mc ab 0.08 pin a1 1. dimensioning and tolerancing methods per asme y14.5m-1994. 2. all dimensions are in millimeters. 3. ball position designation per jesd 95-1, spp-010. 4. e represents the solder ball grid pitch. 5. symbol "md" is the ball matrix in the "d" direction. symbol "me" is the ball matrix in the "e" direction. n is the number of populated solder ball positions for matrix size md x me. 6. dimension "b" is measured at the maximum ball diameter in a plane parallel to datum c. 7. sd and se are measured with respect to datums a and b and define the position of the center solder ball in the outer row. when there is an odd number of solder balls in the outer row sd or se = 0.000. when there is an even number of solder balls in the outer row, sd or se = e/2 8. "+" indicates the theoretical center of depopulated balls. 9. not used. 10. a1 corner to be identified by chamfer, laser or ink mark, metallized mark indentation or other means. package tlb 069 jedec n/a 10.00 mm x 8.00 mm package note symbol min. nom. max. a --- --- 1.20 profile a1 0.20 --- --- ball height a2 0.81 --- 0.97 body thickness d 10.00 bsc body size e 8.00 bsc body size d1 7.20 bsc matrix footprint e1 7.20 bsc matrix footprint md 10 matrix size d direction me 10 matrix size e direction n 69 ball count ob 0.33 --- 0.43 ball diameter ee 0.80 bsc ball pitch ed 0.80 bsc ball pitch sd/se 0.40 bsc solder ball placement a2,a3,a4,a7,a8,a9,b2,b9,b10 depopulated solder balls c1,c10,d1,d10,e5,e6,f5,f6 g1,g10,h1,h10 j1,j2,j9,j10,k2,k3,k4,k7,k8,k9 notes: w052903-163814c
june 10, 2003 am41lv3204m 65 preliminary revision summary revision a (march 21, 2003) initial release. revision a+1 (june 10, 2003) global changed datasheet name to am41lv3204. connection diagram corrected pinout numbering. pin description added ciof and dq15/a-1 trademarks copyright ? 2003 advanced micro devices, inc. all rights reserved. amd, the amd logo, and combinations thereof are regi stered trademarks of advanced micro devices, inc. expressflash is a trademark of advanced micro devices, inc. product names used in this publication are for identification pur poses only and may be trademarks of their respective companies .
66 am41lv3204m june 10, 2003 preliminary

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